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The candidate is an experienced Package Layout or Silicon Physical Layout Engineer that has excellent communication & project management skills and can complete the design task with the least supervision. He/she must be able to work on a fast phase environment and collaborate well with others.
Job Responsibility:
Codesign with Signal/Power Integrity and PCB design team to complete a substrate layout that will meet the design objectives for performance, cost and quality
Support substrate design for probe card substrate, test chips and test vehicles for technology development
Codesign with SOC team to complete Bump matrix and Interposer design for 3D,2.5D, COWOS and other advanced packaging technologies (Chiplet)
Contribute to the development and enhancements of processes and methodologies to improve design efficiency
Interact with Assembly houses and substrate vendors to achieve cost-efficient and high-quality design
Mentor Junior Colleagues to enhance layout practices
Requirements:
Minimum 5 years’ experience in designing complex substrate design or Silicon Interposers
Very good understanding of Signal Integrity and power integrity principles
Knowledge of using CAD Layout tools such as Cadence SIP, APD, Synopsys 3DICC, First Encounter, ICC2 or other Packaging or Silicon Physical Layout Software
B.A. Sc. in Electrical Engineering, Computer Engineering, or Engineering Science
Nice to have:
Knowledge of Python, TCL, Perl or Skill Script Programming is a plus
Experience dealing with assembly, foundry, and substrate vendors