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The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package/Board group, you will work across chip, technology and systems teams to define cost effective and high performance solutions. This is a high visibility position working on custom ASIC packages that include FPGA IP.
Job Responsibility:
Define cost effective and high performance solutions
Understand electrical requirements and translate to the proper package technology requirements
Work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages
Substrate layout design, ballmap assignment in terms of PCB design requirement, high speed interface (PAM-4 112Gbps/high speed DDR) design practices, advanced PKG (2.5D/3D PKG) design knowledge, low-cost PKG solution design including FCCSP, InFO, and thin-core design
Come up with performance metrics for organic package technologies
Translate requirements (Design guidelines, technology, stackup, manufacturing time etc) for various device packaging
Tradeoff PCB Layout guidelines/features to optimize the package ballmap and work with chip team to optimize the die size
Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations
Support substrate layout review and work with layout designer to achieve electrical performance and DFx requirement during the design stage and final design review stage
Requirements:
Bachelors or Masters degree in computer engineering/Electrical Engineering
Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines
Package/PCB layout experience
Experience in high power, Gbs IO products is a plus
Current working Knowledge of Cadence package design tool is a must
knowledge of SKILL is a plus
Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc.
Knowledge on DoE, DFM/DFR is a plus
Good knowledge of SerDes design and package/PCB layout constraints