MTS Silicon Design Engineer

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Develop UVM based verification environment and testbenches, automate processes and flows
• Use AI tools, models extensively to augment SV/UVM test suite for efficient coverage closure
• Use Formal verification techniques at SoC level verification
• Work on SoC UPF power aware verification
• Work on industry-standard cryptographic and security algorithms (e.g., AES, RSA, SHA)
• Work on Functional verification of SoC level Interconnect, NoC architecture design verification
• SoC Performance verification on data paths Band width, Latencies involving coherent/non-coherent paths to DDR
• DFx/DFT infrastructure functional verification
• Build directed and random verification tests targeting functional and code coverage metrics closure
• Work on functional verification of latest standards of high-speed bus protocols like PCIe, USB
• Debug test failures to determine the root cause
• work with RTL and firmware engineers to resolve design defects and correct any test issues
• Add directed or constrain random tests to meet the functional, code coverage requirements

• Bachelors or Masters degree in computer engineering/Electrical Engineering with 7+Yrs of exp
• Proficient in any or all of the following skills: Using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, and C
• Developing UVM based verification frameworks and testbenches, processes and flows
• Knowledge of industry-standard cryptographic and security algorithms (e.g., AES, RSA, SHA)
• Develop UVM based verification environment and testbenches, automate processes and flows
• Use AI tools, models extensively to augment SV/UVM test suite for efficient coverage closure
• Experience in Formal verification techniques at SoC level verification is preferable
• Work on SoC UPF power aware verification
• Knowledge of SoC level Interconnects, NoC architecture designs
• SoC Performance verification on data paths Band width, Latencies involving coherent/non-coherent paths to DDR
• Build directed and random verification tests targeting functional and code coverage metrics closure
• Work on latest standards of high-speed bus protocols like PCIe, USB
• Debug test failures to determine the root cause
• work with RTL and firmware engineers to resolve design defects and correct any test issues
• Desirable DFx/DFT infrastructure functional verification
• Knowledge of ISO26262 Functional safety verification is a plus
• Experience in verifying multimillion gate chip designs from specifications to tape-out
• Excellent communication and presentation skills

• Knowledge of ISO26262 Functional safety verification is a plus
• Desirable DFx/DFT infrastructure functional verification

Benefits offered are described: AMD benefits at a glance