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The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting edge foundry technology. Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signaling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.
Job Responsibility:
Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso
Floorplan, route, and assemble lower-level cells into macros
Build black-box/abstract models and views consumed by other teams
contribute to tapeout collateral for custom blocks
Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners
Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality
Requirements:
Strong understanding of CMOS device/circuit theory and analog/digital layout best practices
Custom layout using Cadence Virtuoso
Physical verification using Mentor/Siemens Calibre (LVS, DRC, PERC) and ERC/EM/IR flows
Scripting/automation in Perl, TCL, SVRF/TVF, SKILL is a plus
Exposure to advanced nodes (e.g., 2nm/3nm
experience at 5nm/7nm also valued)
Background with IP/standard-cell layout, high-speed differential signaling, PLL/DLL/VCO, DACs, power pads, and in-context XOR
Electrical/Mechanical Engineering Degree and/or Electronics related Diploma
Nice to have:
Scripting/automation in Perl, TCL, SVRF/TVF, SKILL
Exposure to advanced nodes (e.g., 2nm/3nm
experience at 5nm/7nm also valued)
Background with IP/standard-cell layout, high-speed differential signaling, PLL/DLL/VCO, DACs, power pads, and in-context XOR