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Memory Subsystem Design and Integration Engineer

Canada, Markham 124000.00 - 186000.00 CAD / Year · Job Posted January 06, 2026
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Job Description

The Memory Subsystem team at AMD is hiring an RTL and Integration Engineer to contribute to the definition, design, development, and integration of high-speed LPDDR/DDR memory subsystem solutions and associated IP. This role spans IP-level RTL development through full subsystem integration and includes close collaboration with architecture, verification, firmware, BIOS, and physical design teams across multiple geographic locations.

Job Responsibility

  • Design, develop, and maintain RTL for memory subsystem IP and integration logic using Verilog/System Verilog
  • Participate in architecture and micro-architecture definition and translate requirements into RTL
  • Integrate IP blocks to build complete DDR/LPDDR memory subsystems
  • Collaborate with verification teams on test plans, debug, and pre-silicon issue resolution
  • Work with physical design teams on timing targets, floor planning, and CDC strategies
  • Analyze and debug complex functional, timing, and integration issues
  • Develop and maintain subsystem documentation and timing diagrams
  • Support pre-silicon and post-silicon bring-up activities

Requirements

  • Experience with DDR/JEDEC standard IP, DDR PHY, memory controllers, or memory subsystems
  • Experience stitching IP blocks to build complete subsystems
  • Knowledge of SVA/OVL and synthesizable assertions
  • Exposure to VCS and/or Zebu emulation
  • Understanding of power management, UPF, and low-power design concepts
  • Strong fundamental and foundational knowledge and application of Object-Oriented Programming concepts
  • Strong proficiency in Verilog and System Verilog for RTL design
  • Experience designing and integrating IP and subsystems in complex SoC environments
  • Understanding of clocking, resets, CDC, and synchronization techniques
  • Ability to debug RTL and integration issues using simulation tools
  • Experience collaborating with verification, firmware, and physical design teams
  • Familiarity with Git and/or Perforce
  • Bachelor’s or master’s degree (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field

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