Mbist Design Engineer Job at Duo Security (Yerevan)

Mbist Design Engineer

Meet the Team Join Cisco’s ASIC Design for Test (DFT) Team, where innovation, c...

Location

Armenia , Yerevan

Salary:

Not provided

Cisco

Expiration Date

Until further notice

Requirements

Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related technical field
2+ years of hands-on experience in MBIST, SCAN/ATPG, and DFT methodologies for complex digital and mixed-signal designs
Proven expertise with industry-standard DFT tools and flows (e.g., Synopsys, Cadence, Mentor)
Strong understanding of ASIC/FPGA design flow, including RTL design, verification, and test
Proficiency in scripting languages such as Tcl, Python, or Perl for test automation and workflow enhancement
Demonstrated ability to identify, analyze, and resolve DFT issues related to MBIST insertion, pattern generation, and fault coverage
Excellent communication skills and experience collaborating within cross-functional engineering teams

Job Responsibility

Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits
Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs
Collaborate Across Teams: Work closely with design, verification, ATE, and physical design teams to ensure DFT structures meet functional, timing, and implementation requirements
Leverage Tools and Automation: Apply and develop automation scripts and in-house tools for DFT workflows, including MBIST pattern generation and fault simulation, using industry-standard EDA solutions
Fault Diagnosis and Debugging: Identify, analyze, and debug issues related to DFT structures, perform root cause analysis on failed tests, and recommend design changes for improved testability
Documentation and Reporting: Prepare detailed documentation on test plans, test coverage, and debugging results
report on DFT metrics to ensure compliance with company and industry standards

Fulltime

Smts Silicon Design Engineer

We are seeking a motivated DFx engineer to join our S3 SOC DFX team. In this rol...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience and understanding of ASIC DFX, synthesis, simulation and verification flow and experience of working in DFX architecture of complex SOC
Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration
Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem
Experience in End-to-End DFX flow development/creation
Expert in at least one of the scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts that provide scalable solutions to DFX implementation
Strong EDA tools experience (Tessent, Design Compiler, Spyglass,)
Proficient in doing basic unit-level verification using simulations
Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required
Exposure to Static timing analysis & Timing closure is required
Scan/ATPG patterns & test flows development, debug, test, and characterization

Job Responsibility

The successful candidate will own/lead the DFX Design architecture and implement cutting edge DFX features including SCAN, ATPG, MBIST, BSCAN, etc.
Work closely with the DFX Architecture and the various IP Design teams to align on the DFX requirements and successfully implement the DFX design
Design and develop correct by construction DFX design and support DFX verification
Work closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects
Work with the Synthesis and PD team to ensure correct DFT implementation and timing closure
Provide post silicon support to ensure successful bring up

Fulltime

Sr. DFT Design Engineer

Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. A...

Location

United States , Austin

Salary:

159200.00 - 215300.00 USD / Year

Amazon Pforzheim GmbH

Expiration Date

Until further notice

Requirements

Bachelor's degree in computer science, electrical engineering, or related field
5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks experience
Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
Experience with automation script development

Job Responsibility

Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals
Mentor and develop junior engineers through code reviews, methodology training, and technical guidance
Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up

What we offer

health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
401(k) matching
paid time off
parental leave
sign-on payments
restricted stock units (RSUs)

Fulltime

Silicon Design Engineer

We are seeking a motivated DFx engineer to join our SBIO design team. In this ro...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Experience in scan stitching and strong knowledge of scan stitching concepts
Exposure to MBIST/BISR implementation and the Synopsys SMS MBIST insertion flow
Excellent hands on ATPG experience and familiarity with ATPG related file requirements
Knowledge or experience with Tessent SSN (Siemens) is a plus
Knowledge of Spyglass DFT
Good in C++ and object-oriented programming concepts
Familiarity with automation scripts such as Perl or Python is a plus
Understanding of JTAG and IJTAG fundamentals
Exposure to AI related work is a plus

Job Responsibility

Implement and verify DFT features such as SCAN, MBIST, and BSCAN
Perform Spyglass DFT bring-up, debug and coverage improvement
Perform scan insertion and ATPG (Traditional, Cell Aware, SSN) pattern generation
Verify ATPG patterns using gate level simulation
Analyze and improve ATPG and DFT DV test coverage
Develop and debug DFT verification tests
Work with the Synthesis and PD team to ensure correct DFT implementation and timing closure
Provide post silicon support to ensure successful bring up

Fulltime

Senior Silicon Design Engineer (DFx)

We are seeking a motivated DFx engineer to join our SBIO design team. In this ro...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Experience in scan stitching and strong knowledge of scan stitching concepts
Exposure to MBIST/BISR implementation and the Synopsys SMS MBIST insertion flow
Excellent hands on ATPG experience and familiarity with ATPG related file requirements
Knowledge or experience with Tessent SSN (Siemens) is a plus
Knowledge of Spyglass DFT
Good in C++ and object-oriented programming concepts
Familiarity with automation scripts such as Perl or Python is a plus
Understanding of JTAG and IJTAG fundamentals
Exposure to AI related work is a plus

Job Responsibility

Implement and verify DFT features such as SCAN, MBIST, and BSCAN
Perform Spyglass DFT bring-up, debug and coverage improvement
Perform scan insertion and ATPG (Traditional, Cell Aware, SSN) pattern generation
Verify ATPG patterns using gate level simulation
Analyze and improve ATPG and DFT DV test coverage
Develop and debug DFT verification tests
Work with the Synthesis and PD team to ensure correct DFT implementation and timing closure
Provide post silicon support to ensure successful bring up

Fulltime

Senior SoC/ASIC Physical Design Engineer

About the Job: We are seeking a highly skilled Senior SoC/ASIC Physical Design E...

Location

United States , Irvine

Salary:

Not provided

Xcelerium

Expiration Date

Until further notice

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (Master’s preferred)
10+ years of experience in ASIC/SoC physical design and flow development
Expertise in RTL-to-GDSII physical design and signoff flows
Strong experience with Synopsys EDA tools, understanding tool capabilities and underlying algorithms
Proficient in physical design methodologies: synthesis, place & route, STA, formal verification, CDC, and power analysis
Knowledge of FinFET and deep sub-micron CMOS technologies, including power dissipation, leakage, and dynamic behavior
Familiarity with DFT, Scan, MBIST, and LBIST methodologies and their impact on physical design
Proficient in scripting languages (Python, Tcl, Perl, bash/csh) and automation using Makefiles
Skilled in extraction and analysis of design parameters, QOR metrics, and implementing voltage scaling (SVS, DVFS) and SRAM split rail architectures
Proven ability to work collaboratively in dynamic environments, lead design closure activities, and drive execution with a proactive, solution-oriented mindset

Job Responsibility

Develop and Implement PD Flow: Establish a modern physical design (PD) flow utilizing the latest EDA tool fusion and machine learning (ML) techniques to maximize PPA efficiency, optimize resource allocation, and achieve industry-leading time-to-closure and tapeout
End-to-End Physical Design Execution: Perform partition synthesis and physical implementation, including synthesis, floorplanning, power/ground grid generation, place & route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks
Methodology and Automation: Create and refine physical design methodologies and automation scripts to streamline implementation and signoff processes
Cross-Functional Collaboration: Work closely with RTL, DFT, and ASIC design teams to define architectural feasibility, establish timing, power, and area targets, and explore design trade-offs
Drive Design Closure: Utilize an objective, metrics-driven approach to resolve design, timing, and flow issues and ensure predictability in achieving project milestones
Signoff Ownership: Lead signoff closure activities, including static timing analysis (STA), noise analysis, logic equivalency, physical verification, and power integrity (EM/IR)

What we offer

We provide competitive compensation package

Design For Test Engineer

We are seeking a experienced Design For Test engineer to join our CPU Cores team...

Location

United Kingdom , Cambridge

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in Scan based testing and industry standard ATPG CAD tools
Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc.
Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools
Experience in MBIST implementation and verification
Good understanding of DFT components like JTAG(IEEE 1149.x), IJTAG(IEEE P1687), Core Test(IEEE P1500), SSN(Streaming Scan Network), SSH, Test Compression, OCC etc.
Excellent Verilog RTL coding, scripting( using Python, Perl, Shell, TCL, Awk, Sed etc) and debugging skills
Good understanding of STA concepts
Experience in Spyglass based DFT DRC checks at RTL level
Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc
Prior experience in working with Version control systems like perforce, git etc

Job Responsibility

Keep abreast with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies in to AMD products
Define and implement DFT architecture and features for next generation multi-core microprocessor designs and support their verification effort
Work closely with architects, design, verification, physical design and product engineering teams to integrate DFT requirements seamlessly into the overall design process and to develop scalable DFT architectures for complex CPU designs
Coordinate with DFT teams across different time zones to develop unified DFT strategies, promoting effective communication and collaboration
Work closely with DFT Tool Vendors and drive improvements based on the testability requirements
Develop efficient DFx flows and methodology compatible with front end and back end design flows
Work with the product, test engineering teams and post-silicon debug teams to ensure successful silicon bring up, to help root-cause any silicon failures and to enhance yield learning & improvement
Mentor and coach junior engineers

Fulltime

DFT Engineer

DFT engineer will lead strong engineering team on Scan, MBIST, iJTAG test develo...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience DFT engineering experience through DFT pre and post silicon cycles
Experience in creating and implementing complex chip-level DFT architecture
Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
Strong MBIST knowledge
Knowledge of Tessent Streaming Scan Network SSN and hand-on experience is a big plus
Proficient in logic design using Verilog and experience in synthesis and STA
Experience in developing test benches and simulation in RTL/GATE/SDF environments
Knowledge of FPGA synthesis and design flow is a plus
Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)

Job Responsibility

Manage DFT engineers resolving technical challenges and meeting product schedule
The role is in AMD global quality and operation organization driving best manufacturing test solution through pre and post silicon activities
Work closely with design teams and make sure DFT structures are correctly implemented
Responsible for developing, implementing and verifying DFT schemes on hard-IPs in AMD ASIC and FPGA products
Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, IEEE1149.1 JTAG and IEEE1687 IJTAG
Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE
Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem
Assist in Diagnosis and Yield enhancement through product lifecycle
Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management

Fulltime

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Mbist Design Engineer

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