Manager Silicon Design Engineering Job at AMD (Hyderabad)

Silicon Design Engineering Manager

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

Taiwan , Hsinchu; Taipei

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Master's degree in Computer Engineering or Electrical Engineering with solid design and leading experiences
Solid digital ASIC/SOC design verification, and manager/leading experiences in the domain
Prior experience in silicon IP design and verification
Prior experience Managing technical teams
Fluent English
Must be a self-starter and self-motivated

Job Responsibility

Lead a high-performance engineering team
Form a team and nurture talent
Lead team, meet IP delivery schedule commitments and provide strong support to SOC
Collaborate with multi-functional leaders to drive AMD's success

Senior Manager Silicon Design Engineering

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
A strong leader with experience working with a distributed team
Strong mentoring and coaching skills
Proven experience managing and leading engineering teams
Prior experience in optimizing performance (client, server, system, or embedded)
Strong system and software engineering background
Strong communications skills
Strong analytic and problem-solving skills
Must be a self-starter and self-motivated
Prior experience Managing technical teams

Job Responsibility

Lead a high-performance engineering team
Form a team and nurture talent
Lead team, meet schedule commitments and provide strong support to customers
Collaborate with multi-functional leaders to drive AMD's success

Senior Manager Silicon Design Engineering

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Strong mentoring and coaching skills
Excellent people skills
Excellent verbal and written communication skills
Strong time management skills
Good understand of Analog Layout
Good understand of Analog Circuits
Able to review Analog Layout PDV results
Attention to detail
Good problem-solving skills

Job Responsibility

People Manager – responsible for Team Members
Career Development
Performance Management
Project Management
Able to manage multiple projects efficiently and effectively
Resource planning
Project scheduling
Project Tracking
Work closely with Engineering staff to ensure correct requirements are achieved
Project status report-out to various stakeholders

Director Silicon Design Engineering

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

~15-25 years of strong experience in SOC
BE/B.Tech/ME/MTECH/MS or equivalent ECE/EEE
Expertise in SOC integration and implementation - IP Integration, SOC fabrics, Voltage and clock domain crossings, Low power design, RTL Quality checks, Clock, Reset, Fuses, Synthesis, Timing Analysis, Design Partitioning and signoff
Strong Problem Solving and Debugging Skills
Comfortable with design/implementation tools and flows like VCS, SOC Connectivity, Spyglass Lint/CDC/RDC, SgLP, Synthesis – DC/FC, etc.
Expertise in SOC architecture, System bus and IO protocol understanding (e.g. AXI, PCIe, Memory etc.)
Good understanding of System integration, multi-die methodology, and system solution
Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks, and mitigation plan
Comfort with Scripting such as Perl, shell, Python and TCL is a plus

Job Responsibility

Work with management / leadership team for SOC planning, schedule, resource demand/supply, critical path analysis, and execution
Driving SOC design execution with local and global team
Driving team to deliver to SOC milestone and ensure all quality metrics are met on time
Work with architecture team on high level arch and uArch definition
Work with IP team for IP requirement, deliverables, and negotiations
Working on all aspects of design execution like IP integration, Lint, CDC, RDC, Low-power implementation, VCLP, Equivalence Check, LEC, Formality, etc
Working with DV team on test plan review, coverage gap analysis and debug failures
Working with PD team on Physical design feedback to meet PD requirement
Driving ECOs to successful implementation
Running regular execution meetings, scrums, standing meetings and resolving bottlenecks

Director, Silicon Design Engineering

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

Taiwan , Hsinchu/Taipei

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

A strong leader with experience working with a distributed team
Strong mentoring and coaching skills
Proven experience managing and leading engineering teams
Prior experience in optimizing performance (client, server, system, or embedded)
Experience managing IP design projects with teams of 10 or more people
Specialized knowledge of USB 3.0/3.1/3.2 or Thunderbolt protocols and link layers is preferred
Knowledge of PCIE or AMBA is a plus
Expertise in IP micro-architecture and Verilog RTL design for large digital IP projects
Recognized as a technical leader who can innovate and work across different projects and departments
Fluent in English speaking, presenting, and writing

Job Responsibility

Lead a high-performance engineering team
Form a team and nurture talent
Lead team, meet schedule commitments and provide strong support to customers
Collaborate with multi-functional leaders to drive AMD's success

Fulltime

System Design & Debug Manager – AI Customer Engineering

This role serves as the debug execution backbone of AMD's AI Customer Engineerin...

Location

United States , Santa Clara

Salary:

186080.00 - 279120.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Deep understanding of data center system architecture (CPU, GPU, FPGA, memory, connectivity, RAS, hotplug)
Familiarity with hardware bring up, validation, manufacturing, and test flows
Knowledge of reliability and quality metrics (yield, DPM, FIT)
Proven years of experience in the semiconductor industry
Deep hands-on experience with silicon debug (pre-silicon and post-silicon)
Strong background in product development, debug tools, validation, failure analysis, or customer engineering
Proven experience managing complex debug programs across multiple customer segments
Strong functional team and project management skills with ability to drive execution across global, cross-functional teams
Excellent written and verbal communication skills, including executive-level engagement
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field required

Job Responsibility

Debug Program Leadership - Lead debug execution across hyperscale, OEM, HPC, and enterprise customer programs. Own high-impact, cross-customer and systemic issues and maintain visibility into top risks and trends
Customer Program Integration - Partner with Customer Program Managers to align debug execution with customer deliverables, platform readiness, and deployment schedules. Support escalations and executive-level customer engagements
Technical Debug Coordination - Drive cross-functional debug efforts across design, validation, product engineering, and failure analysis. Align pre- and post-silicon debug strategies and connect lab debug to real-world customer environments
Field Failure & Fleet Quality Management - Lead resolution of field failures, fleet anomalies, and data center reliability issues. Aggregate fleet, RMA, and production signals and feed learnings back into design, validation, and manufacturing
Governance & Process Improvement - Own debug tracking, prioritization, risk management, and executive reporting. Apply structured methodologies (8D, CAPA, FMEA) and drive continuous improvement in execution speed and consistency

Fulltime

Principal Silicon Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Santa Clara

Salary:

142800.00 - 304200.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check

Job Responsibility

Functional validation of PCIe IP at Block, Cluster or Fullchip using UVM/C test bench and Verification IP (VIP)
Develop Test Plan and write unit tests for functional validation
Create and Manage regression suites, debug failures, and drive timely resolution
Innovate to improve validation efficiency through methodologies and tools
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

What we offer

Certain roles may be eligible for benefits and other compensation

Fulltime

Staff Silicon Design Engineer

We are looking for a MTS Design Verification Engineer who will be part of the pe...

Location

Serbia , Belgrade

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

7+ years of ASIC design verification experience with strong knowledge of RTL design, verification and Architecture
Hands on experience with developing or enhancing UVM testbenches and proficient in UVM and SV concepts
Solid understanding of IP level ASIC design and verification flow from project planning to tape out
Strong experience in debugging functional or performance issues in the design
Hands on experience with scrum planning and execution
Experience with C/C++ and scripting language: Perl, Python, TCL
Strong problem solving skills

Job Responsibility

Technically lead a small team of engineers, responsible for NBIO performance for various projects
Collaborate with performance architects, design and verification engineers to understand the new performance features to be verified
Create test plan documentation, based on use cases defined by hardware designers and architects, coordinate technical reviews within the team
Drive regression triage meetings with team, and drive daily scrum for various projects as well as manage backlogs and planning
Actively involved in developing new ideas to improve the engineering infrastructure, methodology and execution
Provide technical support to the team to debug both functional and performance test failures to determine the problem's root cause
Work with RTL designers and SoC/IP Architects to resolve HW and configuration related performance issues
Analyze and review performance results with SoC/Chip leads and suggest potential solutions
Work on performance case studies with Performance architects, facilitating research through generating results and scripts to analyze results
Write detailed reports to publish performance results and present them in various management readouts

Fulltime

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Manager Silicon Design Engineering

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