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We are seeking a highly motivated and experienced ATE Test Manager to lead Memory Built-In Self-Test (MBIST) development for next-generation AMD SoC products. In this role, you will be responsible for end-to-end test program strategy, execution, and production readiness, spanning pre-silicon development through high-volume manufacturing. The role requires strong technical leadership in MBIST, ATE test methodologies, and cross-functional collaboration across design, DFT, DV, and product engineering teams.
Job Responsibility
Lead and mentor a team of ATE test engineers
Drive alignment across cross-functional stakeholders
Support resource planning, prioritization, and escalation handling during critical phases
Define and implement MBIST test architecture, including FSM, SMS, Latch Array, and ROM BIST flows
Drive MBIST enablement including bitmapping strategies, repair flows and fuse programming, test coverage validation
Collaborate closely with DFT and design teams on test access mechanisms (e.g., JTAG) and MBIST controller configuration and integration
Own ATE test strategy, implementation, and readiness for MBIST from pre-silicon through production ramp and sustaining
Lead development of MBIST ATE test programs, including test flows, methodologies, and infrastructure
Drive test coverage, quality, and cost optimization for wafer sort and final test
Oversee silicon bring-up, debug, characterization, and yield improvement activities
Requirements
Bachelor/Master in Electrical/Electronic Engineering
Experience in the Semiconductor industry
Demonstrated experience in technical leadership or people management roles
Strong DFT and ATE test methodologies
MBIST test pattern development, Pre-silicon simulation and debug experience
Experience with Mentor / Synopsys / Cadence EDA
Strong ATE & test class/method development experience with Advantest 93k and/or T2K platform preferred
Microprocessor architecture and System-on-chip (SOC)