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Low Power Design Verification Engineer

United States, Boxborough 139360.00 - 209040.00 USD / Year · Job Posted January 12, 2026
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Job Description

The focus of this role is to develop, execute, debug tests and methodologies for SoC low power features. You will work closely with the Architecture, IP/SoC Design, Physical Design Teams, and Product Engineers to achieve first pass silicon success.

Job Responsibility

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Build the directed and random verification tests
  • Debug test failures to determine the root cause
  • work with RTL and firmware engineers to resolve design defects and correct any test issues
  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Requirements

  • SoC level ASIC verification experience
  • Experience with multiple SoC tape-outs taken to production
  • Hands on experience of Low Power design and verification methodologies (e.g., UPF, power domains, multi-voltage)
  • NPU/AI processor knowledge
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in developing and using UVM based verification frameworks and testbenches, processes and flows in both Linux and Windows environments
  • Automating workflows in a distributed compute environment
  • Experienced with Assembly, Verilog, System Verilog, C, C++
  • Good understanding and hands-on experience in the UVM concepts
  • Good working knowledge of SystemC and TLM with some related experience
  • Scripting language experience: Perl, Python, Ruby, Makefile, shell preferred
  • Bachelors, Masters or PHD in Computer Science, Electrical Engineering or relevant fields

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