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Lead the definition and implementation of manufacturing test solutions, developing production, characterization, and qualification test programs to ensure reliable, high-performance products for Achronix’s portfolio of FPGAs. Work with design, product, and operation teams to enhance test coverage, optimize test time, and deliver solutions from early silicon bring-up to high-volume manufacturing.
Job Responsibility:
Define and implement DFT architecture (scan, boundary scan, MBIST)
Collaborate with design and physical design teams to ensure integration and verification of DFT features
Design and implement test mode controls and access mechanisms
Generate and validate ATPG patterns for various fault types
Generate test cases targeting specific FPGA blocks and IP
Work with IP vendors to integrate testing solutions for external memory interfaces and high-speed I/O
Perform fault coverage analysis and implement improvements
Conduct gate-level simulations with test patterns
Perform silicon test pattern bring-up, validation, and debugging on lab bench and ATE platforms
Implement and debug scan, BIST, and functional tests on production testers
Conduct comprehensive analysis of yield issues
Develop and maintain scripts to automate pattern generation, simulation, data analysis, and test vector conversion
Maintain and improve internal DFT and test infrastructure workflows
Work with cross-functional teams to ensure testability and deliver high-quality silicon
Requirements:
10+ years of experience in DFT, testing, or silicon validation
Solid understanding of scan insertion, ATPG, MBIST, and fault models
Experience with Synopsys TestMax, Siemens Tessent, and similar DFT EDA tools
Proficiency with JTAG, boundary scan, and related IEEE standards (1149.1, 1149.6)
Hands-on experience with ATPG, MBIST and functional pattern generation, simulation, and verification
Familiarity with script-based test case generators and industry-standard test pattern formats (WGL, STIL)
Proficiency in scripting languages (Python, Perl, or Tcl)
Strong debugging and problem-solving skills for silicon and test issues
Nice to have:
Familiarity with ATE test program development and debugging (Advantest 93K), silicon bring-up, and volume production testing
Knowledge of silicon yield analysis, failure diagnosis, and reliability testing
Understanding of DFT implications for physical design, including scan chain reordering and test mode timing
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