CrawlJobs Logo

Lead Soc Physical Design Engineer

amd.com Logo

AMD

Location Icon

Location:
India , Bangalore

Category Icon
Category:
IT - Software Development

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

Not provided
Save Job
Save Icon
Apply Position

Job Description:

As a member of the Strategic Silicon Solution Group Full Chip Physical Design team, you will help bring to life cutting-edge designs. You will work on Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. This person will be working on Full chip / Sub-system level Physical Design, Timing Analysis, Synthesis, Logical equivalence, Physical Verification, Power design/implementation/signoff, and will act as a mentor/coach/guide to Design Engineers. Will work very closely with Fellows, Principal Engineers, Architects, Technology/CAD teams and collaborate with cross functional worldwide teams.

Job Responsibility:

  • Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis
  • Full chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing
  • Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption
  • Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
  • Full chip / sub-system level constraints, MMMC & cross talk aware timing closure with latest OCV based analysis
  • RTL2GDSII design implementation and flow debug top down or bottoms up at chip level
  • PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia, Fabric cores and/or other critical sub-systems
  • Low Power signoff like Static and Dynamic power analysis at top level and/or sub-system level
  • Full chip / sub system level Clock tree synthesis and advanced clock tree implementation
  • Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence
  • Physical design and timing methodology development on a particular node as well as for a specific SOC
  • Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC

Requirements:

  • Minimum 15+ years of relevant work experience
  • Expertise in ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools
  • Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff
  • Should have worked as a go to person or technical lead for at least few full chip projects
  • Strong technical leadership and ability to mentor/guide/coach design engineers
  • Strong inter-personal skills and ability to collaborate with teams spread across multiple geos
  • Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts
  • Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
  • Experience in 5nm & below technologies
  • Hands-on in reference flows, excellent debugging skills
  • Must have hands on Physical Design experience and must have handled RTL to GDS II at Top level or Hierarchical top level for at least few tape outs
  • Must have led physical design team/s in the capacity of technical lead or as a go to person
  • Highly accurate and detail-oriented, possessing good communication and problem-solving skills

Additional Information:

Job Posted:
March 19, 2026

Icon
AMD - All Job Offers
Job Link Share:
Copy Link Icon
Facebook Icon Twitter Icon LinkedIn Icon

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Lead Soc Physical Design Engineer

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's or master’s in electrical or computer engineering or related field with 15+ years of experience
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeouts of complex ASICs in leading edge technology
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Lead a team in defining implementation and execution plan for a schip/SOC
  • Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
  • Drive the to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
  • Optimizing technology, libraries, physical design, RTL design, and architecture
  • Leading the team in defining the implementation and execution plan for a subchip/SOC
  • Collaborating with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects to ensure a cohesive plan
  • Executing the defined plan to ensure successful tapeout of the subchip/SOC
  • Driving the team to achieve the best performance, power, and area (PPA) for AI system-on-chips
  • Optimizing technology choices, libraries, physical design methodologies, RTL design strategies, and architectural decisions to meet performance targets
  • Ensuring that the physical design aspects align with the overall project goals and timelines
  • Fulltime
Read More
Arrow Right
New

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Mountain View
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level
  • Develop and implement methodologies and strategies to improve physical design efficiency and performance
  • Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing, physical verification, functional logics equivalence, low power verification and electromigration and IR drop
  • Implementation of functional ECO with least physical design impact
  • Design and implement the global clocking scheme at SOC and sub chip levels
  • Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies
  • Installation and quality check of internal and external IP collaterals for use by Physical Design execution team
  • Conduct physical design reviews, identify and resolve design issues, and provide guidance to junior engineers
  • Fulltime
Read More
Arrow Right
New

Sr. Physical Design Engineer

We are looking for an adaptive, self-motivative design Physical design engineer ...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 7+ years of experience in Physical Design
  • Hands on Place and Route experience
  • Experience in one of the signoff aspects of PD (e.g., timing or physical verification)
  • Experience with testchip floorplan and physical verification is preferred
  • Should have worked on lower technology nodes
  • Should have worked on 3-4 tapeouts
  • Bachelors or Masters degree in electronics engineering/Electrical Engineering
Job Responsibility
Job Responsibility
  • Physical Design closure of critical partitions in the leading IPs that goes into multiple SoCs
Read More
Arrow Right

Senior Manager Silicon Design Engineer

AMD seeks a passionate, collaborative leader with strong technical skills and th...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 12-15 years full-time experience in IP hardware design
  • Proven experience managing and leading engineering teams
  • Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
  • Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
  • Clock domain crossing (CDC) tools
  • Detailed understanding of SoC design flows
  • Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating
  • Outstanding interaction skills while communicating both written and verbally
  • Ability to work with multi-level functional teams across various geographies
  • Outstanding problem-solving and analytical skills
Job Responsibility
Job Responsibility
  • Lead a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies
  • Help bring to life cutting-edge designs, working closely with architecture, physical design, and product engineers to achieve first pass silicon success
  • Design of IP and subsystems with integration of AMD and other 3rd party IPs
  • Work collaboratively with other members of the IP team to support design verification, implementation, synthesis, constraints, static timing analysis, and delivery to SOC
  • Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up
Read More
Arrow Right

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Ability to provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
  • Bachelor's or master’s in electrical or computer engineering or related field with 10+ years of experience
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeout of complex ASICs in leading edge process node technology
  • 8+ years of hands-on experience in EDA vendor tools such as Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal
Job Responsibility
Job Responsibility
  • Lead a team in defining implementation and execution plan for a schip/SOC
  • Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
  • Drive the team to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
  • Optimizing technology, libraries, physical design, RTL design, and architecture
  • Collaborate with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects
  • Provide technical guidance and mentorship to team members
  • Oversee the development and implementation of physical design flows and methodologies
  • Collaborate with cross-functional teams to address design challenges and optimize for manufacturability
  • Monitor progress, identify risks, and implement mitigation strategies
  • Keep abreast of the latest industry trends, tools, and techniques in physical design
  • Fulltime
Read More
Arrow Right
New

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Mountain View
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeouts of complex ASICs in leading edge technology
  • Experience in leading team to deliver planned PD goals
Job Responsibility
Job Responsibility
  • Lead and execute Physical Design activities at block, sub-chip, and full-chip levels
  • Contribute to Physical Design flow development, automation, and methodology improvements
  • Evaluate and recommend technology nodes, IP selection, EDA tools, and vendor solutions
  • Provide clear and concise status updates on progress, risks, and mitigation plans to management
  • Operate independently with minimal supervision while maintaining strong attention to detail
  • Support program needs, including occasional travel as required
  • Drive all phases of implementation including: Floorplanning
  • Synthesis
  • Placement and optimization
  • Clock Tree Synthesis (CTS) and custom clocking
  • Fulltime
Read More
Arrow Right

Technologist, ASIC Development Engineering

We are looking for a highly skilled and experienced individual for SoC PD lead p...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
  • A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs
  • Proven ability in technically leading a small/medium-sized team for executing projects preferred
  • Hands-on experience on the entire PD Flow from RTL to GDSII
  • Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains
  • Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)
  • Exposure to static timing analysis fixes including automated ECO generation
  • Strong in areas on CTS, Power, Bump planning, Floorplan
  • Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies
  • Library preparation in any environment (Synopsys, Cadence, etc)
Job Responsibility
Job Responsibility
  • To be responsible for leading RTL-to-GDSII SoC implementation effort
  • To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc.
  • To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity
  • To ensure process compliance during project execution and enable / participate in technical discussions/reviews
  • To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
  • Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow
  • Foster a culture of innovation, collaboration, and continuous improvement
  • Fulltime
Read More
Arrow Right

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
  • 9+ years of experience in digital design, with a focus on RTL design for complex SoCs
  • Deep expertise in Verilog/SystemVerilog
  • Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
  • Experience with synthesis, static timing analysis, and DFT concepts
  • Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
  • Proven track record of leading technical teams and delivering successful silicon
  • Excellent analytical, problem-solving, and communication skills
  • Passion for innovation and delivering high-quality, scalable solutions
Job Responsibility
Job Responsibility
  • Define and review SoC architecture and design specifications
  • Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
  • Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
  • Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
  • Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
  • Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
  • Contribute to IP selection, evaluation, and integration in SoC designs
  • Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels
  • Fulltime
Read More
Arrow Right
Jobs by Category
Art and Entertainment Jobs Banking Jobs Call Center Jobs Construction Jobs Consulting Jobs Customer Service Jobs Education Jobs Energy Jobs Finance Jobs Gastronomy Jobs Health and Beauty Jobs Hospitality and Tourism Jobs Human Resources Jobs Insurance Jobs IT - Administration Jobs IT - Software Development Jobs Legal Jobs Logistics Jobs Manufacturing Jobs Marketing, Digital Marketing, SEO, SEM Jobs Media Jobs Nursing Jobs Office Administration Jobs Pharmacy Jobs Physical Work Jobs Public Relations Jobs Public Sector Jobs Purchasing Jobs Quality Control Jobs Real Estate Jobs Research and Development Jobs Sales Jobs
Job Positions Jobs by Country
United States Jobs United Kingdom Jobs India Jobs Canada Jobs Australia Jobs Germany Jobs Ireland Jobs Poland Jobs
Company
Blog About Us Contact
Follow Us
Facebook
X (Twitter)
LinkedIn
Instagram
CrawlJobs Group
ITFlashcards AllDevBlogs
© 2026 CrawlJobs Ltd. All Rights Reserved
Terms & Conditions Privacy Policy