Lead Silicon Design Engineer Job at AMD (Hyderabad)

Staff Silicon Design Engineer

We are looking for a MTS Design Verification Engineer who will be part of the pe...

Location

Serbia , Belgrade

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

7+ years of ASIC design verification experience with strong knowledge of RTL design, verification and Architecture
Hands on experience with developing or enhancing UVM testbenches and proficient in UVM and SV concepts
Solid understanding of IP level ASIC design and verification flow from project planning to tape out
Strong experience in debugging functional or performance issues in the design
Hands on experience with scrum planning and execution
Experience with C/C++ and scripting language: Perl, Python, TCL
Strong problem solving skills

Job Responsibility

Technically lead a small team of engineers, responsible for NBIO performance for various projects
Collaborate with performance architects, design and verification engineers to understand the new performance features to be verified
Create test plan documentation, based on use cases defined by hardware designers and architects, coordinate technical reviews within the team
Drive regression triage meetings with team, and drive daily scrum for various projects as well as manage backlogs and planning
Actively involved in developing new ideas to improve the engineering infrastructure, methodology and execution
Provide technical support to the team to debug both functional and performance test failures to determine the problem's root cause
Work with RTL designers and SoC/IP Architects to resolve HW and configuration related performance issues
Analyze and review performance results with SoC/Chip leads and suggest potential solutions
Work on performance case studies with Performance architects, facilitating research through generating results and scripts to analyze results
Write detailed reports to publish performance results and present them in various management readouts

Fulltime

Senior Silicon Design Engineer

Push Boundaries, Deliver Innovation and Change the World! In this role you will ...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Good understanding on ASIC/SOC design verification flow with SV/UVM/Formal Verification
Good experiences with simulation model creation and testbench build (better with UVM)
Good logical thinking and expression
Good cooperation cross teams
Bachelors or Masters degree in Computer Engineering/Electrical and Electronics Engineering
X86/ARM/8051 architecture
AMBA(AXI/AHB/APB) bus
PCIe protocol
f/w writing and debug experience
experience to co-work with f/w team for f/w sequence define in embedded design

Job Responsibility

Apply current functional verification techniques to perform and improve pre-silicon IP verification quality and product Time to Market for ASIC/SOC design
Technically involve in the porting/creation of the DV environment for the new design
block and IP level test plan creation and implementation
coverage analysis
regression cleanup
Work independently on various DV tasks and providing technical guidance to the DV team
lead a big DV task inside team or cross team

What we offer

AMD benefits at a glance

Fulltime

Senior Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING: At AMD, our mission is to build great pro...

Location

United Kingdom , Belfast

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor’s, Master’s, or PhD in Electronic Engineering, Computer Science, or a related field
Hands on experience in ASIC/SoC design
Strong expertise in Verilog/SystemVerilog (or VHDL)
Proven experience delivering complex digital hardware systems to silicon
Solid understanding of microarchitecture and hardware/software trade-offs
Experience with industry-standard ASIC design, simulation, and synthesis flows
Strong debugging, analytical, and problem-solving skills

Job Responsibility

Lead the design and delivery of complex ASIC blocks for data center networking silicon
Contribute to and influence architecture definition and microarchitecture decisions
Translate system requirements into detailed specifications and high-quality RTL implementations
Work closely with verification, physical design, and validation teams to ensure first-silicon success
Drive quality, power, and area optimization across the design
Mentor junior engineers and contribute to engineering best practices
Collaborate across global teams to align on technical direction and execution

Fulltime

Senior Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great pro...

Location

United Kingdom , Penicuik

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor's, Master's, or PhD in Electronic Engineering, Computer Science, or a related field
10+ years of experience in ASIC/SoC design
Strong expertise in Verilog/SystemVerilog (or VHDL)
Proven experience delivering complex digital hardware systems to silicon
Solid understanding of microarchitecture and hardware/software trade-offs
Experience with industry-standard ASIC design, simulation, and synthesis flows
Strong debugging, analytical, and problem-solving skills

Job Responsibility

Lead the design and delivery of complex ASIC blocks for data center networking silicon
Contribute to and influence architecture definition and microarchitecture decisions
Translate system requirements into detailed specifications and high-quality RTL implementations
Work closely with verification, physical design, and validation teams to ensure first-silicon success
Drive quality, power, and area optimization across the design
Mentor junior engineers and contribute to engineering best practices
Collaborate across global teams to align on technical direction and execution

Fulltime

Silicon Design Engineer

AMD's VBU - Virtual Bring-Up Central Methodology team, is a seasoned engineer fo...

Location

Canada , Markham

Salary:

155200.00 - 232800.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Background in emulation or prototyping, familiarity with flows and infrastructure
Development skills in Python/Perl, C/C++, Verilog, Unix shell
Proficiency in Unix environment, administrative level preferred
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Design and develop efficient solutions targeting AMD emulation and prototyping efficiency
Work with EDA vendors to implement best practices to ensure most optimal flows
Develop solutions to ensure emulator workload execution performance tracking for the leading-edge performance/throughput
Evaluate, implement and help to improve FPGA-based technologies and platforms
Analyze and improve multitude of data, collected through emulation
Contribute to testbench development and improvement
Be true part of the great team, priding itself in collaborative, supportive and open culture

Fulltime

Senior Silicon Design Engineer

This role will focus on planning, micro architect, documenting, code and debug t...

Location

Romania , IASI

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience with digital circuits and the ability to synthesize small circuitry
Experience with Verilog Hardware description Language is highly desirable
Good understanding of how a microprocessor/microcontroller works and how such devices can be interfaced with various peripherals like memories and io devices
Good understanding on cache coherency protocols is desirable
Proficient in debugging firmware and RTL code using simulation tools
Exposure to leadership or mentorship is an asset
Excellent communication skills & teamwork experience is highly desirable
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be designed
Micro architect the feature, document it, estimate the effort and review the implementation with RTL lead and verification team
Execute the RTL code of the new feature at best quality and within the estimated duration
Debug and fix the RTL bugs, fix timing, area and power consumption issues
Debug support for SOC simulation, emulation and actual silicon bring-up in lab
Analyze code coverage and detect holes in the verification environment

Fulltime

Pmts Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great pro...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

14–18+ years of semiconductor design experience
Strong hands‑on RTL design and microarchitecture ownership, with designs that progressed through PD and tapeout
Direct experience working within or closely alongside Physical Design teams
Deep understanding of SDC intent, timing, clocking, partitioning, and physical closure trade‑offs
Proven ability to resolve PD issues through architectural and RTL‑level solutions, not late physical workarounds
Experience driving or contributing to shift‑left initiatives or early physical feasibility analysis
Comfort operating as a senior technical authority, making cross‑domain engineering decisions
Exposure to AI‑assisted or highly automated design flows is a strong plus
Own creation and maintenance of physical‑aware RTL to enable PNR hierarchy, including partitioning, feedthroughs, repeaters, and physical intent insertion
Partner with SOC Design to translate logical IP integration into physical‑aware RTL and with IP design team creation digital‑on‑top RTL wrappers for analog IPs

Job Responsibility

Own Physical Design shift‑left strategy, ensuring PD risks are identified at RTL, SDC, and paper‑floorplan stages
Act as chief engineering authority for AI‑assisted and automated PD execution, defining where AI can act autonomously and where human judgment is required
Bridge RTL, microarchitecture, and PD, translating early PD findings into architectural and RTL‑level corrective actions
Define and enforce PD readiness and quality bars across synthesis, PnR, STA, and physical closure
Lead predictive closure and risk management, using early indicators to forecast timing, ECO churn, and execution complexity
Govern signoff readiness, ensuring AI‑augmented flows never compromise correctness or confidence
Codify execution playbooks and best practices to reduce variability and scale high‑quality PD execution across teams
Serve as a trusted technical peer to RTL architects, PD leads, and AI/methodology owners

Fulltime

PMTS Silicon Design Engineer

We are seeking a seasoned SoC Architect with expertise or significant interest i...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Excellent foundation in NoC architecture and CPU/GPU coherency
Preferred expertise in ARM/other core architecture
Preferred CHI protocol experience
Experience analyzing NoC Fabric, CPU, or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture and logic design
Excellent communication skills
Ability to lead team technically
Bachelors or Masters degree in computer engineering/Electrical Engineering
Expertise in coherent fabric architecture, interfacing with different CPU cores - ex:x86 and/or ARM
Excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings

Job Responsibility

Define Data Fabric/NoC features and capabilities required to meet SoC requirements on power, performance, Area targets
Close architecture and micro-architecture requirements, drive technical specifications for data fabric and its IP blocks to meet those requirements, and provide technical direction to execution teams
Lead discussions on ARM/x86 core interfacing to AMD data fabric IPs, to match SoC requirements
Lead design on one or more domains for the data fabric implementation
Work with architects and design leads to identify and assess complex technical issues/risks and develop as well as implement solutions to achieve product requirements
Knowledge sharing and mentoring
Work closely with Design teams for Area refinement, Timing targets, Verification Test plan reviews, Pre-Si bug resolution and Performance/Power Verification sign offs
Work closely with Verification teams to ensure quality component development
Support Post-Si teams for functional issues debug/resolution

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Lead Silicon Design Engineer

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