Lead RTL Design Engineer Job at Cerebras Systems (Sunnyvale)

CPU Architecture and RTL Design Lead Engineer

Drive the definition, implementation (RTL design), and integration of Clocking, ...

Location

Ireland , Cork

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proficiency with Verilog HDL
Understanding of Clock/Power Domain Crossing concepts
Understanding of Power Management concepts
Understanding of modern CPU architecture
Eagerness to learn and grow as a CPL design engineer
Collaborate effectively towards the success of the project
Demonstrate a responsive track record of engaging with a diverse set of teams and across a broad set of technical areas
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Collaborate with a dedicated team of engineers to define and implement CPL microarchitecture for AMD CPUs
Reliably deliver a design from concept through tapeout
Drive design closure gaining experience with Static Timing, CDC/Gate CDC, and Static Power analysis
Identify customer challenges and insert a compelling AMD value proposition to address challenges
Make technical contributions and innovations that enable high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs

Rtl Design Lead - Ip Design

As a member of the Computing and Graphics Group, you will help bring to life cut...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

8-12 years full-time experience in IP hardware design
Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
Clock domain crossing (CDC) tools
Detailed understanding of SoC design flows
Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating
Experience with embedded processors and data fabric architectures (NoC)
Outstanding interaction skills while communicating both written and verbally
Ability to work with multi-level functional teams across various geographies
Outstanding problem-solving and analytical skills

Job Responsibility

Design of IP and subsystems with integration of AMD and other 3rd party IPs
Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs
Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up

What we offer

AMD benefits at a glance

Fulltime

Senior RTL Design Lead

We are seeking a seasoned Principal design engineer with expertise or significan...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Excellent foundation in fabric/transport architecture and coherency
Experience in memory design/cache design
Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
Excellent communication, management, and presentation skills
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

Job Responsibility

Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, Area targets
Digital design implementation and micro-architecture of components of the Infinity Data Fabric, including cache design
Micro-architecture and RTL coding in Verilog/SystemVerilog
Lead design on one or more domains
Work with architects and design leads to identify and assess complex technical issues
Work closely with verification teams to ensure quality component development
Work closely with Physical design to ensure quality PPA targets
Post silicon support to ensure successful bring up
Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams
Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power

Rtl Design Engineer

This exciting position in AMD's Silicon IP solutions & SOC group will provide th...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

A minimum of 8 years of experience is required
Proven experience in Silicon IP development process, methodologies, Design for Test methodologies
Experience with Verilog RTL design, VCS simulation tool, Perl/Shell scripting
Proven experience in contributing to complex silicon tapeouts
Detailed understanding and proven track record of developing any of the leading edge PCIe, Full featured DMAs, NVMe based Storage IP, networking IP solutions such as Ethernet, TCP/IP, RDMA IPs
Strong oral and written communication skills are essential
The ideal candidate will be a proactive contributor to the RTL design methodologies
Ability to work on complex issues where analysis situations or data requires an in-depth evaluation of variable factors
To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups
A Bachelor of Science Degree in Electrical Engineering or Computer Science, a master’s degree or equivalent experience is required

Job Responsibility

Define u-architecture from the architecture definition
Evaluating and executing design and development plans for IPs
RTL design, IP Integration & documentation
Participating in and acting as a senior technical reviewer for various u-architecture and implementation reviews within the development organization
Working with stakeholders to develop comprehensive testing plans including Compliance and Interop testing
Critically Review and provide feedback on the Design Implementations and Verification plans
Acting as technical mentor to junior engineers

Senior RTL Design Engineer – Accelerator IP

Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Enginee...

Location

United States , Austin

Salary:

117000.00 - 175000.00 USD / Year

Ericsson

Expiration Date

Until further notice

Requirements

Several years of RTL design in complex ASIC/IP environments
Expert SystemVerilog/Verilog skills
End-to-end ASIC flow mastery: coding, linting, CDC, synthesis, timing closure
Proven ability to distill DSP, FEC, or other L1 processing algorithms into high-performance hardware
Equally comfortable deep-diving into code and shaping high-level architecture strategies
A collaborative powerhouse who thrives in an intense, creative, close-knit environment

Job Responsibility

Transform high-level architectural vision into blazing-fast, reliable RTL (SystemVerilog/Verilog)
Take complete ownership of major IP blocks—specification, microarchitecture, RTL creation, synthesis, and delivery
Act as the go-to technical lead for verification, backend/PD, and architecture teams
Drive optimizations to balance power, area, and throughput without compromising innovation
Lead critical design decisions that steer the next generation of telecom hardware

What we offer

Choice of three medical plan options
Dental plan option
Company credits for medical and dental premiums
Ericsson US 401(k) Plan with automatic 3% company contribution and matching
Company credits for basic life insurance, basic accidental death and dismemberment coverage, short-term and long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
Minimum of 15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time

Fulltime

RTL Design Engineer

Role: RTL Design Engineer. What candidate will Be Doing: Strong expertise on Art...

Location

United States Of America , San Jose

Salary:

160000.00 - 180000.00 USD / Year

Arrow Electronics

Expiration Date

Until further notice

Requirements

Strong expertise on Arteris Design Toolset (Like Mansour Amirfathi)
At-least 5+ years of experience in Verilog Design
AMBA AXI bus along-with ARM or C based processor
Ensure customer satisfaction
Reporting to customers on daily or weekly progress effectively
NOC Architecture awareness
PCIe System Expertise: Deep understanding and hands-on experience in PCIe system architecture, with an emphasis on physical layer design and specification
Ensure compliance with PCIe specifications, including but not limited to PIPE interface, LTSSM, 8b/10b and 128b/130b encoding, EIEOS intervals, equalization and electrical idle conditions
Deep understanding of PCIe retimer specification
Lead silicon bring-up activities, troubleshoot, and debug PCIe related issues

What we offer

Medical, Dental, Vision Insurance
401k, With Matching Contributions
Short-Term/Long-Term Disability Insurance
Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
Paid Time Off (including sick, holiday, vacation, etc.)
Tuition Reimbursement
Growth Opportunities

Fulltime

Lead Hardware Design Engineer

We are looking for a Lead hardware design engineer with a broad skill set and a ...

Location

United Kingdom , Melbourn

Salary:

Not provided

PA Consulting

Expiration Date

Until further notice

Requirements

A proven track record of developing elegant electronic system architectures and implementing designs using a professional workflow
Well versed in a breadth of core electronics disciplines including analogue and digital circuit design and associated EDA techniques
An excellent understanding of key embedded technologies including microcontrollers, SoCs, SoMs and maybe FPGA
Alongside hardware development skills, we look for strong embedded software, RTL or other related skills
Exposure to the full product lifecycle from concept generation through to product release including demonstrable experience of delivering your designs into service
Possession of a good understanding of the regulatory landscape of the UK, EU and US and a proven track record of designing for compliance with appropriate standards
Excellent written and verbal communication skills and be comfortable explaining complex engineering concepts to both a technical and non-technical audience
Degree qualified – a good degree in electronic engineering or a related subject from a leading university
The ability to gain UK SC security clearance if not already acquired (in practice, this requires sole UK nationality)
Someone not afraid to be ‘Hands-on’ and work with the team to work through challenges from first principles on the bench

Job Responsibility

developing solutions at the system level as well as take on the detailed electronic design work required to realise your concept
Work across the whole development lifecycle for clients, offering a rare opportunity to gain broad experiences from concept to delivery

What we offer

Health and lifestyle perks accompanying private healthcare for you and your family
25 days annual leave (plus a bonus half day on Christmas Eve) with the opportunity to buy 5 additional days
Generous company pension scheme
Opportunity to get involved with community and charity-based initiatives
Annual performance-based bonus
PA share ownership
Tax efficient benefits (cycle to work, give as you earn)

Fulltime

Lead Soc Physical Design Engineer

As a member of the Strategic Silicon Solution Group Full Chip Physical Design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Minimum 15+ years of relevant work experience
Expertise in ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools
Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff
Should have worked as a go to person or technical lead for at least few full chip projects
Strong technical leadership and ability to mentor/guide/coach design engineers
Strong inter-personal skills and ability to collaborate with teams spread across multiple geos
Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
Experience in 5nm & below technologies
Hands-on in reference flows, excellent debugging skills

Job Responsibility

Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis
Full chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing
Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption
Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
Full chip / sub-system level constraints, MMMC & cross talk aware timing closure with latest OCV based analysis
RTL2GDSII design implementation and flow debug top down or bottoms up at chip level
PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia, Fabric cores and/or other critical sub-systems
Low Power signoff like Static and Dynamic power analysis at top level and/or sub-system level
Full chip / sub system level Clock tree synthesis and advanced clock tree implementation
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence

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Lead RTL Design Engineer

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