CrawlJobs Logo

Lead Platform Emulation Engineer

India, Bangalore · Job Posted March 21, 2026
Apply Position
Job Link Share

Job Description

AMD is seeking a Platform Emulation Software Engineer to join our Data Center GPU organization. Our products support the rapidly scaling Data Center and High-Performance Compute infrastructure. You will be an integral member of the Platform Emulation team responsible for: Designing and implementing GPU applications in CUDA/C++ to enhance pre-silicon verification; Writing tools to improve the efficiency of debugging hardware on emulation; Building and executing GPU benchmarks/applications on the emulator; Developing emulation infrastructure and tools. You will work alongside a team of innovative engineers to support the deployment of AMD’s Instinct ML products targeting Supercomputers and Data Center workloads.

Job Responsibility

  • Design and implement GPU applications in CUDA/HIP to enhance pre-silicon verification
  • Develop tools and automation to improve the efficiency of debugging hardware on emulation
  • Run and collect data for analysis on AMD’s high-end emulators and simulation models
  • Develop scripts/tools to parse and analyze data from emulation runs
  • Run and collect functional and performance data for AI/ML workloads
  • Collaborate with senior engineers to support debug of hardware-related failures and performance issues observed on emulation
  • Attend weekly meetings, provide status communication, and deliver technical presentations

Requirements

  • Strong knowledge of computer hardware architecture (GPU/CPU, memory hierarchy, interconnects, caches)
  • Excellent programming skills in C, C++
  • Excellent programming skills in Python
  • Excellent programming skills in Tcl
  • Experience or understanding of shared memory concurrent programming
  • Experience or understanding of relaxed memory models
  • Experience or understanding of cache coherency
  • Working knowledge of Linux/Unix environments and shell scripting
  • Knowledge of computer software architecture and boot flow (boot code, BIOS, device drivers, OS)
  • Excellent oral and written communication skills
  • Willingness to learn and think outside the box

Nice to have

  • Exposure to Verilog/SystemVerilog and waveform-based debug
  • Experience with ML workloads and profiling/performance analysis
  • Familiarity with APIs/platforms such as ROCm, OpenCL, OpenGL, Vulkan

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Similar Jobs for

Lead Platform Emulation Engineer

8 matching positions

Lead Platform Emulation Engineer

The focus of this role is to plan, build, execute the verification, validation/e...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience
  • Experience with BIOS/OS bring up on full X86 SOC emulation platform
  • Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem
  • Proficient in debugging firmware and RTL code using simulation tools
  • Good understanding of PCIe/USB/Ethernet standards
  • safety concepts/IPs
  • Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC
  • SOC design model build experience
  • Experienced with Verilog, System Verilog, C, and C++
  • Experience in writing and debugging testbenches
Job Responsibility
Job Responsibility
  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models
  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Build the directed Pre-Silicon Emulation tests
  • Debug test failures to determine the root cause
  • work with RTL and firmware engineers to resolve design defects and correct any test or infra issues
  • Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment
  • Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation
  • Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug
Read More
Arrow Right
New

Platform Soc Debug Lead Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great prod...
Location
Location
United States , Austin
Salary
Salary:
200000.00 - 300000.00 USD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Strong understanding of Server platform components, x86 or other complex CPU architectures
  • Deeper domain expertise in areas such as IO interfaces - PCIe, CXL, RAS, Power management to drive comprehensive system level test-plan execution
  • Understanding of BMC firmware and features, including IPMI, Redfish, sensor monitoring, power control, and remote management is a plus
  • Prior experience with computer system design and/or validation, testing tools, and environments
  • Experience with handling and taking captures using Oscilloscopes, protocol analyzers, and JTAG based Debug Tools
  • Proficiency in C, Python, and shell scripting for low-level development and debug
  • Excellent organizational skills and the ability to prioritize multiple workstreams and meet tight deadlines
  • Strong networking and relationship-building skills, with the ability to drive effective decision-making across various functions and levels within the organization
  • Knowledge of pre-silicon environments (Verification, Emulation, Virtual Bring-Up) is a plus
  • BS or MS degree in Electrical Engineering or related major, with 12+ years of applicable experience
Job Responsibility
Job Responsibility
  • Lead platform and SoC debug for EPYC/AI server platforms, driving issue resolution, validation, and quality to meet program milestones
  • Lead debugging efforts for enabling AI/Server SoC platforms in domains such as high-speed data-center I/O (PCIe, CXL, etc.), RAS features to resolve issues efficiently that are seen from the program execution
  • Collaborate with partner organizations to provide root cause analysis for platform issues in a Data center environment
  • Improve debug capabilities and methodology over time by identifying common challenges or impediments to efficient debug and working with partner organizations like design, Firmware and software teams to drive innovation in silicon architecture, design, tools and methods
  • Manage and track technical issues, risks, and priorities effectively with the business unit and SW Debug tools teams
  • Manage customer and executive communications, including program status, risks and opportunities
  • Maintain strong communication skills, both verbal and written, to convey summary findings and recommendations to senior management
  • Fulltime
Read More
Arrow Right

Debug Lead Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great prod...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Highly skilled engineering professional with over 15 years of experience
  • Solid experience in both Pre and Post Silicon enablement and validation with strong BIOS/FW/SW intercepting knowledge
  • Solid Experience and Knowledge in the HW and FW aspects of X86 design
  • Solid experience in connecting the bigger picture across different related domains between Hardware/Firmware and Software and com
  • Adept in calling out risks while anticipating issues and coming up with appropriate mitigation plans
  • Experienced in working with the Enablement Manager and Leads, Program Managers, Product Managers, BIOS/FW Managers and other cross functional stakeholders and create a robust alignment setup while running execution
  • Preferred experience working with cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW
  • Experience in High Speed I/Os like PCIe (preferably Gen4 and above), Memory (DDR4/DDR5.LPDDR4/LPDDR5), USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces and Ethernet and high-speed interconnects
  • Experience in Power Management
  • Hands-on high speed and board measurement techniques in using high end equipment like Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers, etc
Job Responsibility
Job Responsibility
  • Assume technical responsibility from Pre-silicon to Post-silicon environment for Feature enablement and SoC-System level flow for use cases
  • Pre-Silicon: New SOC features enablement, implementation and coverage plan in Emulation
  • Pre-silicon: Review all Silicon bugs that deferred out SOC Tape out and ensure it does not impact the system level features / use cases
  • Post Silicon: Lead the Bring-up planning in collaboration with Silicon teams, Platform, Firmware / BIOS, Post Si Validation team so we have the fastest and functional bring-up as soon as silicon arrives in the lab
  • Post Silicon: Partner with SOC NPI PM and be the technical lead to support & debug SOC related challenges from Tape out all the way to SOC IP milestone
  • Post Silicon: Lead cross-functional critical silicon issue debug, uplevel and communicate the updates into core teams and Management program reviews
  • Post Silicon: Provide inputs to Silicon Validation teams on coverage for New SOC features, enablement, implementation, IPs, and functional coverage at the system level
  • Exhibit strong technical leadership on X86 architecture and associated feature implementation
  • Exhibit great technical depth in the post silicon enablement and validation of both HW and FW aspects to take the right technical decisions for the team
  • Synergize with the Pre-silicon and DV teams and other stakeholders for proper interception of milestones and risk callouts
  • Fulltime
Read More
Arrow Right

ASIC Engineer, Emulation

Engineers with experience in HW emulation and prototyping required to build ASIC...
Location
Location
United States , Sunnyvale
Salary
Salary:
146000.00 - 209000.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ Years of experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments
  • Experience with current emulation technologies and methods, simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods
Job Responsibility
Job Responsibility
  • Deliver high-quality emulation and prototyping models on industry-standard emulation and prototyping platforms
  • Design, build, and execute comprehensive emulation test plans to ensure model accuracy and support pre-silicon validation efforts
  • Lead the development and adoption of best-in-class emulation methodologies to accelerate hardware verification and software development
  • Collaborate with Design, DV, validation, and software teams to develop tools, flows, and mechanisms that demonstrate key performance indicators such as functionality, performance, and power efficiency
  • Enhance and mature standard interfaces including PCIe, DDRx, USB, and other interfaces on emulation components such as speed bridges, transactors, and virtual components
  • Continuously improve the efficiency and effectiveness of emulation components and workflows for testing, debugging, analysis, and automation
  • Partner with vendors to troubleshoot issues, deploy new emulation capabilities, and drive ongoing improvements
What we offer
What we offer
  • bonus
  • equity
  • benefits
Read More
Arrow Right

Lead Diagnostics Software Engineer, ATE Integration

Location
Location
Canada , Markham
Salary
Salary:
156000.00 - 234000.00 CAD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proven industry experience in silicon engineering spanning post-silicon validation, product engineering, diagnostics development, or structural/functional test generation
  • Strong programming background in C/C++ and Python, with a concrete understanding of bare-metal or driver-level programming, registers, firmware interactions, and system memory maps
  • Proven hands-on experience with production-grade Automated Test Equipment platforms (e.g., V93000, UltraFLEX) and structural/functional testing at the wafer sort or final test level
  • Expert understanding of structural pattern generation, vector timing, clock domains, and diagnostic patterns (such as functional vectors, BIST/MBIST, or scan compression output)
  • Familiarity with high-volume manufacturing challenges unique to data center architectures, including high-power profiles, HBM integration, and multi-die chiplet interconnect protocols (e.g., UCIe, proprietary fabrics)
  • Deep understanding of GFX and compute architectures, with proven ability to design and implement diagnostic and test cases that maximize coverage and proactively identify silicon issues early
  • Understanding of AI/ML principles and some experience in applying LLM & ML models in applications
  • Experience with working in DevOps environment like GitHub, CI/CD pipelines
  • Excellent problem-solving abilities with a keen eye for detail are highly valued
  • Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Job Responsibility
Job Responsibility
  • Define the technical roadmap, architecture, and deployment strategy for migrating post-silicon SLT and functional GFX IP feature diagnostics onto wafer sort and ATE hardware configurations
  • Architect and develop software utilities/pipelines to convert functional diagnostic sequences, register configurations, and compute workloads into cycle-accurate vector formats (e.g., STIL, WGL, or proprietary tester formats) compatible with high-end ATE testers
  • Serve as the primary technical liaison between the GFX/Compute Diagnostics team, Product/Test Engineering, and Design-for-Test (DFT) teams
  • Analyze existing platform-level hardware/software dependencies (such as sideband management interfaces, firmware, and power management behaviors) to build deterministic, tester-friendly models that emulate host behaviors on ATE hardware
  • Optimize tester execution times (test cost reduction) while maximizing structural and functional test coverage for data center GPU IPs, focusing on massively parallel compute pipelines, high-bandwidth memory (HBM) controllers, and matrix math engines
  • Fulltime
Read More
Arrow Right

Lead Diagnostics Software Engineer, ATE Integration

As the semiconductor industry pivots toward complex chiplet architectures and hy...
Location
Location
United States , Austin
Salary
Salary:
174400.00 - 261600.00 USD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proven industry experience in silicon engineering spanning post-silicon validation, product engineering, diagnostics development, or structural/functional test generation
  • Strong programming background in C/C++ and Python, with a concrete understanding of bare-metal or driver-level programming, registers, firmware interactions, and system memory maps
  • Proven hands-on experience with production-grade Automated Test Equipment platforms (e.g., V93000, UltraFLEX) and structural/functional testing at the wafer sort or final test level
  • Expert understanding of structural pattern generation, vector timing, clock domains, and diagnostic patterns (such as functional vectors, BIST/MBIST, or scan compression output)
  • Familiarity with high-volume manufacturing challenges unique to data center architectures, including high-power profiles, HBM integration, and multi-die chiplet interconnect protocols (e.g., UCIe, proprietary fabrics)
  • Deep understanding of GFX and compute architectures, with proven ability to design and implement diagnostic and test cases that maximize coverage and proactively identify silicon issues early
  • Understanding of AI/ML principles and some experience in applying LLM & ML models in applications
  • Experience with working in DevOps environment like GitHub, CI/CD pipelines
  • Excellent problem-solving abilities with a keen eye for detail are highly valued
  • Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Job Responsibility
Job Responsibility
  • Define the technical roadmap, architecture, and deployment strategy for migrating post-silicon SLT and functional GFX IP feature diagnostics onto wafer sort and ATE hardware configurations
  • Architect and develop software utilities/pipelines to convert functional diagnostic sequences, register configurations, and compute workloads into cycle-accurate vector formats (e.g., STIL, WGL, or proprietary tester formats) compatible with high-end ATE testers
  • Serve as the primary technical liaison between the GFX/Compute Diagnostics team, Product/Test Engineering, and Design-for-Test (DFT) teams
  • Analyze existing platform-level hardware/software dependencies (such as sideband management interfaces, firmware, and power management behaviors) to build deterministic, tester-friendly models that emulate host behaviors on ATE hardware
  • Optimize tester execution times (test cost reduction) while maximizing structural and functional test coverage for data center GPU IPs, focusing on massively parallel compute pipelines, high-bandwidth memory (HBM) controllers, and matrix math engines
  • Fulltime
Read More
Arrow Right

Lead x86 BIOS/UEFI/coreboot development Engineer

Exciting opportunity within the Embedded BIOS development team working on latest...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 13+ years of experience in the x86 BIOS/UEFI/coreboot development
  • Exposure to pre-silicon BIOS development in a simulation/emulation environment
  • Exposure to Emulation environments like Synopsis-Zebu-ZS5/Cadence-Palladium/Siemen-Veloce
  • Experience with x86 CPU/APU architectures and associated compilation tools
  • Expert in C language
  • knowledge of x86 assembly
  • Experience with platform bring-up
  • Familiar with at least one BIOS code base (AMI, Insyde, coreboot or Phoenix BIOS) and also FSP development experience
  • Hands on experience with hardware debugging tools like AMD HDT, ITP, Arium, etc.
  • Able to read and interpret hardware schematics
Job Responsibility
Job Responsibility
  • Responsible for BIOS and pre-OS driver development including design, documentation, unit testing and debug for pre and post silicon support
  • Apply a data minded approach to target optimization efforts
  • Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture
  • Design and develop new groundbreaking AMD technologies
  • Participating in new ASIC and hardware bring ups
  • Debugging/fix existing issues and research alternative, more efficient ways to accomplish the same work
  • Develop technical relationships with peers and partners
Read More
Arrow Right
New

Ip Post-Silicon Validation Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING  At AMD, our mission is to build great pro...
Location
Location
Canada , Markham
Salary
Salary:
155200.00 - 232800.00 CAD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's or master’s degree majoring in EE, CS or related field
  • Experience in digital logic design/verification/post-silicon validation
  • Extensive experience with ASIC debug techniques and methodologies
  • Knowledge of physical and protocol levels of common high-speed interfaces such as PCIe/CXL/UALINK is an asset
  • Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization
  • Strong scripting skills (eg. Ruby, Python)
  • Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
  • In-depth knowledge of PC architectures/PCIe protocol is an asset
  • Must have excellent written and verbal communication skills
  • Must excel in a dynamic team working environment
Job Responsibility
Job Responsibility
  • Driving the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs
  • Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s
  • Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives
  • Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs
  • Engaging on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features
  • Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives
  • Developing knowledge of system architecture/debug and other internal IP’s
  • Supporting issues on customer platforms as requested by customer support teams
  • Fulltime
Read More
Arrow Right