Lead IP Verification Engineer Job at AMD (Hyderabad)

DDR Lead Verification Engineer

The focus of this role is to plan, build, and execute the verification of new an...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proficient in IP level ASIC verification
Proficient in debugging RTL code using simulation tools
Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is added advantage
ASIC design verification experience with 7+Years
Hands on experience in developing complex UVC
Good debugging skill and good knowledge of verification tool and methodology
Hands on experience with coverage planning, coding, and coverage closure
Should have worked on developing testplan at module level/IP level /Chip-level project
Mentoring Juniors and ensuring that the team achieves technical goals with high quality
Scripting language experience: Perl, Ruby, Makefile, shell preferred

Job Responsibility

Collaborate with architects, hardware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Fulltime

Senior Lead Verification Engineer (Leadership role)

The Infinity Fabric transport layer verification team is looking for an experien...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proficient in IP or Sub-system level ASIC verification
Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
Exposure to RTL design, software development, formal verification, or other related domains
Experience in UVM TestBench Development for complex designs preferred
15+ years of industry experience is preferred
Bachelor’s or master’s degree in Electronics or Electrical or Computer engineering

Job Responsibility

Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture
Understand TestBench Architecture and develop expertise in TestBench Verification Components
Mentor junior engineers

GPU/GFX IP - Verification Lead

We are currently seeking a highly skilled verification engineer for GFX Verifica...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Min 8 years of experienced in ASIC verification
Must be proficient in Verilog and System Verilog language
Must be good at C/C++ programming and working in Linux and Windows environments
Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and do test plan, test creation and triage, coverage, and assertion etc
Be proficient of script language like Perl, Python
Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail
Must have good English hearing, speaking, reading, and writing capabilities
Must have good teamwork and interpersonal skills
Must be a self-starter, and able to independently drive tasks to completion
Good teamwork and communications skills are required

Job Responsibility

Working with all partners such as lead architects and block design teams to understand features to be implemented and verified
Developing robust test plan for both synthetic testing and real workload trace
Debug verification test failures, working with the design team to accurate defects
Make sure AMD next generation GFXIP can meet performance/power/function expectation

Senior DDR IP Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
5+ years of pre-silicon subsystem or IP verification experience
3+ years of DDR subsystem verification experience
Demonstrated experience in verifying memory controller, DDR PHY, and/or at DDR sub-system level including integration verification of memory controller IP with DDR PHY and Electronic Design Automation (EDA) vendor sourced Dual In-line Memory Module (DIMM) Verification IP (VIP)
Deep understanding of JEDEC spec including mode registers, timing parameters, refresh operations, initialization, calibration, training, power management, and error handling
Experience with verification for a full product cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking
Aptitude for writing scripts/software with industry standard languages like Python
Experience applying generative AI to day-to-day tasks
Ability to meet Microsoft, customer and/or government security screening requirements

Job Responsibility

Own or lead verification of one or more aspects/features of a memory controller Intellectual Property (IP) and/or Double Data Rate (DDR) subsystem integration with Physical Layer (PHY)
Learn about the design and interact with partner teams to define verification strategies and test plans
Develop verification environments and run and debug simulations to drive quality
Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
Innovate to improve verification efficiency through methodologies or tools
Apply industry leading generative AI solutions to verification work
Coach and mentor others in your areas of expertise
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Fulltime

Lead verification Engineer - high speed protocol

This exciting position in the AMD Data Center Networking Technology Solutions gr...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Masters/ Bachelors in EE/EC/CS with 5+ years of experience in IP/SoC/ASIC Verification
Understanding product specifications and deriving the TB architectures
Developing verification plan, test plan, coverage plan, assertions
Developing block level and multi block level verification environments & reusable verification components based on SV/UVM methodology
Coverage metrics to ensure conformity, running regressions, debug test failures and regression management
Knowledge and working experience with any of the complex protocols like PCIe/Ethernet/DMAs/Cryptography/Others – an advantage
Experience in Scripting languages like Perl or Python
Knowledge in AMBA AXI, APB..etc - an advantage
Ability to work collaboratively with other team members and have good ownership and accountability
Assisting validation teams with on board-level test issues, educating design teams on verification methodology

Job Responsibility

Take an independent verification role in developing TB architecture definition and TB infrastructure/test coding development for Data Center Networking IP/Systems
Work as part of a team which is responsible for IP, Subsystem, Systems design verification in the data center networking domains
Participate in providing inputs during solution architecture
Responsible for creating the initial product verification methodology, selecting the testing environments, and developing testing plans to test functionality, performance

Lead Soc Verification Engineer

The focus of this role is to plan, build, and execute the verification of new an...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM
Familiarity with Verilog and General Logic Design concepts
Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR4/DDR5, and peripherals such as USB, PCIe and Ethernet
Knowledge of industry‑standard cryptographic and security algorithms (e.g., AES, RSA, SHA)
Strong working knowledge of UNIX environment and scripting languages such as Perl or Python
Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM/XCELIUM, Verdi, QUESTASIM
Experience using UNIX Revision Control tools - ICM manage, CVS, Perforce and bug tracking tools such as JIRA
Experience in verifying multimillion gate chip designs from specifications to tape-out
Excellent communication and presentation skills
Demonstrate the ability to work with cross-functional teams

Job Responsibility

Develop/Maintain tests for functional verification at SOC level
Build testbench components to support the next generation IP
Maintain or improve current verification libraries to support SOC/Full-chip level verification
Provide technical support to other teams
Help Hardware emulation team to port the RTL to Palladium/Zebu or HAPS/Protium platforms.

Fulltime

New

Formal Verification Engineer

The Formal Verification team is dedicated to formal verification. It provides fo...

Location

Canada , Markham

Salary:

155200.00 - 232800.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Combined ASIC/FPGA design and verification experience
Verify complex IPs including I/O virtualization, PCIe Root Complex/End Point, and high-speed inter-chiplet interconnects using advanced formal verification methodologies
Develop and execute formal functional and security verification strategies to ensure industry-leading design quality and coverage
Apply expertise in high-speed I/O protocols, IP verification, and formal verification technologies to validate next-generation semiconductor designs
Drive adoption of cutting-edge formal verification and automation techniques to improve verification efficiency and accelerate closure
Provide technical leadership, mentorship, and methodology guidance across formal verification projects and teams
Demonstrate strong hands-on experience with AI-based formal verification, including AI-assisted property generation, proof optimization, coverage analysis, root-cause debugging, and verification closure
Collaborate closely with architecture, RTL design, DV, and silicon teams from concept through tapeout and post-silicon validation
Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC), and/or academic formal methods
Expertise in a formal property language (SVA preferred), abstraction techniques, formal sign-off and commercial formal tools (VC-Formal, JasperGold, Questa Formal, etc.)

Job Responsibility

Collaborating with architects and designers to understand the design intents
Creating and executing formal verification plans for design blocks
Writing and debugging properties to verify the design, analyzing signatures and pushing for the resolution
Optimizing runtime using formal techniques
Collecting and reporting status and progress
Improving formal setups based on feedbacks from reviews, metrics, etc
Leading and coordinating verification activities for a small team
Training and coaching junior engineers
Developing working procedures, flows and infra
Handling complicated formal problems

What we offer

Benefits offered are described: AMD benefits at a glance

Fulltime

Principal Silicon Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

142800.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
successful candidate will be required to provide either proof of their country of citizenship or proof of their US residency or other protected status
successful candidate's citizenship will be verified with a valid passport

Job Responsibility

Own the development of C and C++ based test content at the subsystem and SoC levels
Build and maintain the C test infrastructure that the broader team relies on
Own the pre-silicon verification strategy and execution for one or more security IP blocks and subsystems
Architect and extend SystemVerilog and UVM environments that host C-based stimulus
Drive coverage signoff across functional, code, and power-aware coverage
Act as verification lead and technical point of contact for customer and partner teams
Mentor and guide less experienced engineers
Improve verification efficiency by building reference and prediction models, automation, and debug tooling in Python and other scripting languages

What we offer

Benefits and other compensation

Fulltime

Select Country

Lead IP Verification Engineer

Job Responsibility

Requirements

Nice to have

Looking for more opportunities?