CrawlJobs Logo
AMD Logo AMD · IT - Software Development

Lead IP Verification Engineer

India, Hyderabad · Job Posted May 30, 2026
Apply Position
Job Link Share

Job Responsibility

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Build the directed and random verification tests
  • Debug test failures to determine the root cause
  • work with RTL and firmware engineers to resolve design defects and correct any test issues
  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Requirements

  • Proficient in IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches and working in Linux and Windows environments
  • Experienced with Verilog, System Verilog, C, and C++
  • Graphics pipeline knowledge
  • Strong knowledge in AXI, ACE Protocols
  • Strong Knowledge in any of Ethernet, PCIe, USB is needed
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Strong background in the C++ language, preferably on Linux with exposure to Windows platform
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
  • Good working knowledge of SystemC and TLM with some related experience
  • Bachelors or Masters degree in computer engineering/Electrical Engineering with 7+Yrs of exp

Nice to have

  • Exposure to leadership or mentorship is an asset
  • Desirable assets with prior exposure to video codec system or other multimedia solutions
  • Scripting language experience: Perl, Ruby, Makefile, shell preferred
AMD - All Job Offers

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Suggested Tags: Frontend Developer Secretary Talent Manager Salesforce Administrator Data Analyst
Similar Jobs for

Lead IP Verification Engineer

8 matching positions

Lead IP/SOC Verification

In this high-profile role, the Lead IP/SOC Verification will be the overall desi...
Location
Location
United States , Folsom
Salary
Salary:
171200.00 - 256800.00 USD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Experience focused on IP and/or SOC verification with successful completion of multiple ASICs that are in production
  • Requires proven track record in technical leadership. This includes planning, execution, tracking, verification closure, and delivery to programs
  • Requires strong experience with development of UVM, SystemVerilog, C/C++ and Scripting Languages
  • Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
  • Good understanding of code and functional coverage, ability to influence coverage improvement with design and verification teams
  • Good understanding of requirements management, documentation management, and defect management
  • Ability to grasp concepts during discussions and turn minutes into action items
  • Able to communicate concepts and processes with stakeholders
  • Analytical, self-motivated, organized, detailed-oriented and results-oriented
  • Excellent interpersonal skills including the ability to work well with multiple people and teams, ability to communicate progress to team members on a regular basis
Job Responsibility
Job Responsibility
  • Closely work with designers and architect to come up with features, verification and execution plans
  • Own and lead verification quality for GFXIP projects
  • Engage with IP and SOC teams to drive closure to verification strategy
  • Working with architects and verification leads and driving quality test plan specifications
  • Collaborate with architects, hardware engineers, and firmware engineers to understand the complex features and impact to System level/SOC environment
  • Developing verification strategy, infrastructure and needed improvements
  • Driving Pre and post Si verification closure to meet schedule with quality
  • Leading Post Si verification activities to drive triage with FW, SW, IP, SOC and various teams. Plug holes appropriately to improve quality of the IP
  • Working with each domain (sub-system) lead and guide them to get better quality and verification outcome
  • Automating workflows in a distributed compute environment
  • Fulltime
Read More
Arrow Right

ASIC Digital Design Engineering Lead

Idaho Scientific designs and deploys secure system solutions through novel CPU d...
Location
Location
United States , Boise; Salt Lake City
Salary
Salary:
Not provided
idahoscientific.com Logo
Idaho Scientific
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship (no exceptions)
  • Proven work experience designing and fabricating an ASIC (no exceptions)
  • Ability to get a security clearance
  • Solid technical background with at least 5 years of experience in FPGA or ASIC product development
  • Team leadership experience
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • Extreme attention to detail
Job Responsibility
Job Responsibility
  • Lead a team of digital design engineers to create a security system on a chip
  • Collaborate with team members and across teams to explore and clearly identify real problems and solutions
  • Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
  • Integrate complex systems that instantiate both Idaho Scientific and third party IP
  • Contribute to all aspects of design success from specification to production
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world
  • Define and improve high-quality design methods and processes
  • Mentor and guide other ASIC design engineers
What we offer
What we offer
  • Competitive Pay
  • Flexible Work Schedule
  • Health Benefits and Insurance
  • Retirement fund contributions
  • Profit Sharing
  • Generous Paid Time Off Policy
  • Fulltime
Read More
Arrow Right

Lead Test Development Engineer

Lead the definition and implementation of manufacturing test solutions, developi...
Location
Location
United States , Santa Clara
Salary
Salary:
Not provided
achronix.com Logo
Achronix Semiconductor
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 10+ years of experience in DFT, testing, or silicon validation
  • Solid understanding of scan insertion, ATPG, MBIST, and fault models
  • Experience with Synopsys TestMax, Siemens Tessent, and similar DFT EDA tools
  • Proficiency with JTAG, boundary scan, and related IEEE standards (1149.1, 1149.6)
  • Hands-on experience with ATPG, MBIST and functional pattern generation, simulation, and verification
  • Familiarity with script-based test case generators and industry-standard test pattern formats (WGL, STIL)
  • Proficiency in scripting languages (Python, Perl, or Tcl)
  • Strong debugging and problem-solving skills for silicon and test issues
Job Responsibility
Job Responsibility
  • Define and implement DFT architecture (scan, boundary scan, MBIST)
  • Collaborate with design and physical design teams to ensure integration and verification of DFT features
  • Design and implement test mode controls and access mechanisms
  • Generate and validate ATPG patterns for various fault types
  • Generate test cases targeting specific FPGA blocks and IP
  • Work with IP vendors to integrate testing solutions for external memory interfaces and high-speed I/O
  • Perform fault coverage analysis and implement improvements
  • Conduct gate-level simulations with test patterns
  • Perform silicon test pattern bring-up, validation, and debugging on lab bench and ATE platforms
  • Implement and debug scan, BIST, and functional tests on production testers
  • Fulltime
Read More
Arrow Right

Senior DDR IP Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
  • 5+ years of pre-silicon subsystem or IP verification experience
  • 3+ years of DDR subsystem verification experience
  • Demonstrated experience in verifying memory controller, DDR PHY, and/or at DDR sub-system level including integration verification of memory controller IP with DDR PHY and Electronic Design Automation (EDA) vendor sourced Dual In-line Memory Module (DIMM) Verification IP (VIP)
  • Deep understanding of JEDEC spec including mode registers, timing parameters, refresh operations, initialization, calibration, training, power management, and error handling
  • Experience with verification for a full product cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
  • Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking
  • Aptitude for writing scripts/software with industry standard languages like Python
  • Experience applying generative AI to day-to-day tasks
  • Ability to meet Microsoft, customer and/or government security screening requirements
Job Responsibility
Job Responsibility
  • Own or lead verification of one or more aspects/features of a memory controller Intellectual Property (IP) and/or Double Data Rate (DDR) subsystem integration with Physical Layer (PHY)
  • Learn about the design and interact with partner teams to define verification strategies and test plans
  • Develop verification environments and run and debug simulations to drive quality
  • Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
  • Innovate to improve verification efficiency through methodologies or tools
  • Apply industry leading generative AI solutions to verification work
  • Coach and mentor others in your areas of expertise
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion
  • Fulltime
Read More
Arrow Right

Principal Verification Engineer

This position is an excellent opportunity for an experienced and highly motivate...
Location
Location
United Kingdom , Manchester; Cambridge
Salary
Salary:
Not provided
arm.com Logo
ARM
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Experience in working with constrained-random verification including ownership of a suitably complex verification environment and creating testbenches
  • Experience developing reusable and scalable code whilst having in-depth knowledge of SV-UVM
  • Strong scripting skills – being able to develop scripts to support new and existing flows
  • Solid software engineering skills including understanding of object-oriented programming, data structures, and algorithms
  • Familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process
  • Prior technical and/or team leadership skills required for more senior positions
Job Responsibility
Job Responsibility
  • Verification ownership of unit level or multi-unit hierarchy or alternatively verification lead of an overall IP (ISP, Display, Video)
  • Architecting verification IP and full verification environments
  • Reviewing and assessing proposed design changes from a verification complexity point of view
  • Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug
  • Identify cross Media IP process or methodology improvement opportunities, implementing changes to advance hardware verification efficiency
  • Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system
  • Mentor & support other members of the team
What we offer
What we offer
  • Health and Wellness
  • Work and Life Success
  • Financial Rewards
  • Development and Support
Read More
Arrow Right

Staff/Principal Verification Engineer - Video

This position is an excellent opportunity for an experienced and highly motivate...
Location
Location
United Kingdom , Manchester; Cambridge
Salary
Salary:
Not provided
arm.com Logo
ARM
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Experience in working with constrained-random verification including ownership of a suitably complex verification environment and creating testbenches
  • Experience developing reusable and scalable code whilst having in-depth knowledge of SV-UVM
  • Strong scripting skills – being able to develop scripts to support new and existing flows
  • Solid software engineering skills including understanding of object-oriented programming, data structures, and algorithms
  • Familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process
  • Prior technical and/or team leadership skills required for more senior positions
Job Responsibility
Job Responsibility
  • Verification ownership of unit level or multi-unit hierarchy or alternatively verification lead of an overall IP (ISP, Display, Video)
  • Architecting verification IP and full verification environments
  • Reviewing and assessing proposed design changes from a verification complexity point of view
  • Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug
  • Identify cross Media IP process or methodology improvement opportunities, implementing changes to advance hardware verification efficiency
  • Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system
  • Mentor & support other members of the team
What we offer
What we offer
  • Health and Wellness
  • Work and Life Success
  • Financial Rewards
  • Development and Support
  • Fulltime
Read More
Arrow Right

ASIC Verification - Team Lead

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Santa Clara
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Experience working with large verification projects, including cluster/subsystem and fullchip environments
  • Ability to lead large scale verification execution, driving multiple senior level verification engineers across geographic regions towards project completion
  • Develop comprehensive pre-silicon verification test plans based on design specifications and performance requirements
  • Create and maintain UVM/SystemVerilog-based testbenches for block-level, cluster-level, fullchip and emulation verification
  • Comfortable and experienced with AI based tools to accelerate productivity
Job Responsibility
Job Responsibility
  • Pre-Silicon Verification
  • Improves verification efficiency through new and updated methodologies or tools
  • Defines verification strategies and test plans
  • Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels
  • Drives the development of verification environments, runs, and debugs simulations to drive quality
  • Influences the product life cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
  • Leads application of random-stimulus, coverage, formal verification, or other verification techniques to find bugs and meet test plan goals
  • Performance
  • Works collaboratively with various teams to define performance modeling requirements and ensure technology development planning meets needs
  • Determines type of performance model needed and appropriate model fidelity
  • Fulltime
Read More
Arrow Right

ASIC DDR Verification Engineer

At AMD, our mission is to build great products that accelerate next-generation c...
Location
Location
India , Hyderabad
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proven track record in technical leadership of teams with 5+ engineers including planning, execution, tracking, verification closure, and delivery to programs
  • Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS
  • Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
  • Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management
  • BS w/ 7+ yrs or MS w/ 5+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering or Computer Science
Job Responsibility
Job Responsibility
  • Lead the verification of high-speed Crypto/ cutting-edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance
  • Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level
  • Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs
  • Develop and execute comprehensive verification plans, including testbenches and test cases
  • Collaborate with design, architecture, and software teams to define and implement verification strategies
  • Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification
  • Mentor and guide junior engineers, fostering a collaborative and innovative team environment
  • Fulltime
Read More
Arrow Right