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Lead Diagnostics Software Engineer, ATE Integration

Canada, Markham Employment contract 156000.00 - 234000.00 CAD / Year · Job Posted May 29, 2026
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Job Responsibility

  • Define the technical roadmap, architecture, and deployment strategy for migrating post-silicon SLT and functional GFX IP feature diagnostics onto wafer sort and ATE hardware configurations
  • Architect and develop software utilities/pipelines to convert functional diagnostic sequences, register configurations, and compute workloads into cycle-accurate vector formats (e.g., STIL, WGL, or proprietary tester formats) compatible with high-end ATE testers
  • Serve as the primary technical liaison between the GFX/Compute Diagnostics team, Product/Test Engineering, and Design-for-Test (DFT) teams
  • Analyze existing platform-level hardware/software dependencies (such as sideband management interfaces, firmware, and power management behaviors) to build deterministic, tester-friendly models that emulate host behaviors on ATE hardware
  • Optimize tester execution times (test cost reduction) while maximizing structural and functional test coverage for data center GPU IPs, focusing on massively parallel compute pipelines, high-bandwidth memory (HBM) controllers, and matrix math engines

Requirements

  • Proven industry experience in silicon engineering spanning post-silicon validation, product engineering, diagnostics development, or structural/functional test generation
  • Strong programming background in C/C++ and Python, with a concrete understanding of bare-metal or driver-level programming, registers, firmware interactions, and system memory maps
  • Proven hands-on experience with production-grade Automated Test Equipment platforms (e.g., V93000, UltraFLEX) and structural/functional testing at the wafer sort or final test level
  • Expert understanding of structural pattern generation, vector timing, clock domains, and diagnostic patterns (such as functional vectors, BIST/MBIST, or scan compression output)
  • Familiarity with high-volume manufacturing challenges unique to data center architectures, including high-power profiles, HBM integration, and multi-die chiplet interconnect protocols (e.g., UCIe, proprietary fabrics)
  • Deep understanding of GFX and compute architectures, with proven ability to design and implement diagnostic and test cases that maximize coverage and proactively identify silicon issues early
  • Understanding of AI/ML principles and some experience in applying LLM & ML models in applications
  • Experience with working in DevOps environment like GitHub, CI/CD pipelines
  • Excellent problem-solving abilities with a keen eye for detail are highly valued
  • Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field

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