IP Validation Design Engineer Job at AMD (Vancouver)

USB IP Validation Engineer

This technical role is Client Post-Silicon features IO validation and enablement...

Location

China , Shanghai

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Solid understanding of x86 architecture, including system-level components and interactions
Strong knowledge of USB & PCIe Spec and protocol (e.g., USB 2.0/3.x/USB4. TBT)
Hands-on experience in system-level and/or IP-level validation (post-silicon)
Experience with debug and issue root-cause, including use of common debug tools (Windows ETL, logic analyzers, protocol analyzers, waveform viewers, etc.)
Familiarity with Linux operating system, including basic shell usage, scripting, and driver/application bring-up
Experience with pre-silicon verification/validation environments (e.g., simulation, emulation, FPGA prototyping) or post-silicon validation labs
Experience with validation frameworks, test infrastructure
Knowledge of system-level performance, power, and reliability validation concepts for I/O subsystems
Good verbal and written communication skills in English

Job Responsibility

Perform USB IP /PCIe functional validation at system level and IP/block level in pre-silicon and/or post-silicon environments
Develop validation plans, test cases, and test environments based on design specifications and architecture documents
Execute validation tests, analyze results, and ensure comprehensive coverage for USB IP and related system components
Validate and debug features and interoperability involving USB and PCIe subsystems on x86-based platforms
Work closely with design, architecture, firmware, and software teams to identify root-cause, and resolve functional issues
Participate in automation and improvement of validation flows, AI tools, and methodologies
Execute and drive success of programs with multiple projects on the goal

IP Validation Engineer - Machine Learning Accelerators

As a Machine Learning IP Validation Engineer at Meta Reality Labs, you will work...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

Principal IP Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Job Responsibility

Contribute to Security IP Roadmap Design: translate system/security architecture goals into project plans, milestones, and deliverables across multiple IP blocks/subsystems.
Hands-on Design Lead: Design leads for large subsystems or complex IP cores.
Drive end-to-end delivery of Security IP RTL and integration: oversee micro-architecture → RTL implementation → FE customer integration program needs (schedule + quality)
Enforce design quality and signoff rigor: define/optimize processes, best practices, and quality checks (e.g., lint/CDC/RDC-style hygiene, release criteria) to achieve “first-time-right” outcomes.
Embed “security as a product feature” into engineering execution: drive threat-informed design decisions, security posture accountability, and crisp communication of risks/priorities to stakeholders and leadership.
Predictable Execution: Track execution using ADO Tasks and ensure we are on track vs the plan.
Customer Obsessed: Partner with customers to ensure clean collaboration and feedback informing design execution, ensuring highest possible customer satisfaction.

Fulltime

Design Verification Engineer - Internal IP

We are seeking a Design Verification Engineer to join our Internal IP DV team. Y...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

Proficiency with UVM and SystemVerilog
Strong debugging and problem-solving skills for complex digital designs
Solid knowledge of computer architecture and digital design fundamentals
Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics

Job Responsibility

Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems)
Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks
Debug complex datapath and protocol issues in RTL and testbench environments
Work closely with architects and designers to validate functionality and design intent
Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage
Contribute to reusable DV infrastructure, coverage models, and methodology improvements

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

Design Verification Engineer - Interface IP

We are seeking a Design Verification Engineer to join our Interface IP DV team. ...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

5+ years of design verification experience
Experience digging deep into complex verification challenges and finding creative ways to expose corner-case bugs
Hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches
Comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
Thrive in a fast-paced startup environment and can take ownership of projects with minimal direction
Collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights

Job Responsibility

End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
Understand vendor IP configurations and handle handshake with internal IP team
Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications
Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture
Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

Ip Post-Silicon Validation Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great pro...

Location

Canada , Markham

Salary:

155200.00 - 232800.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Bachelor's or master’s degree majoring in EE, CS or related field
Experience in digital logic design/verification/post-silicon validation
Extensive experience with ASIC debug techniques and methodologies
Knowledge of physical and protocol levels of common high-speed interfaces such as PCIe/CXL/UALINK is an asset
Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization
Strong scripting skills (eg. Ruby, Python)
Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
In-depth knowledge of PC architectures/PCIe protocol is an asset
Must have excellent written and verbal communication skills
Must excel in a dynamic team working environment

Job Responsibility

Driving the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs
Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s
Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives
Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs
Engaging on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features
Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives
Developing knowledge of system architecture/debug and other internal IP’s
Supporting issues on customer platforms as requested by customer support teams

Fulltime

Senior Staff Silicon Design Engineer (Design Verification)

At AMD, our mission is to build great products that accelerate next-generation c...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in ASIC/SoC design
Strong hands-on verilog development experience, familiar with scripting languages like Perl
Good experience on complicate hub,control IP design
Strong problem solving, independent thinking, teamwork and communication skills
Bachelor or Master degree in E&E or Computer Engineering. (Preferred Master Degree)

Job Responsibility

Own part of IP feature design with cooperation with other designers
As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.

What we offer

AMD benefits at a glance.

Fpga Developer / Fpga Design Engineer (4g/5g Radio – Datapath / Ru Fpga Design)

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

Hands-on DSP (Digital Signal Processing) expertise including FFT, Beamforming, and Digital Filter implementation
Strong MATLAB / Simulink experience
SystemVerilog and RTL design experience for complex FPGA-based systems
Experience developing FPGA IP and architectures for 4G/5G Radio Units
Knowledge of AXI and Ethernet protocols
Experience with FPGA development tools including Altera Quartus and MATLAB/Simulink
Exposure to model-based design methodologies and FPGA implementation workflows
Understanding of wireless communications, 4G/5G radio architecture, O-RAN, LTE, eCPRI, CPRI, and PTP protocols is desirable but not mandatory
Experience optimizing FPGA resource utilization, timing closure, and high-performance datapath processing
Knowledge of high-speed interfaces such as Ethernet, PCIe, JESD204B/C, AXI, and SERDES technologies

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IP Validation Design Engineer

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