IP Designer Job at IGG Canada (Jakarta)

New

IP Design Supervisor

Location

Indonesia , Jakarta

Salary:

Not provided

IGG Canada

Expiration Date

Until further notice

Requirements

Minimum of 3 years of professional experience in IP design
Minimum of 3 years of team management experience, with demonstrated success in managing the full lifecycle of mature IP derivative product development
Strong global commercialization mindset for IP development, with the vision to create cross-generational IPs that resonate with international audiences
Proficiency in English is required
Exceptional leadership, communication, and collaboration skills

Job Responsibility

Lead and manage a team of 5–10 IP designers
Oversee the development of original IP projects, including character design, emoji/sticker packs, comics, short animations, storyline development, and world-building
Direct and coordinate secondary creation (derivative content) initiatives to expand the IP's reach and longevity
Establish and optimize design workflows and standards to ensure high-quality and efficient output
Coordinate cross-functional resources and manage project prioritization to achieve business objectives
Cultivate and enhance the team's creative capabilities
Define and guide the creative direction, with a primary focus on healing-style (wellness/comfort) or abstract IP designs
Drive innovation to develop distinctive and emotionally resonant IP properties that appeal to a global audience

Network IP Manager

The selected individual will be a part of our Communications team and will be re...

Location

United States , Fort Morgan

Salary:

Not provided

Robert Half

Expiration Date

Until further notice

Requirements

Demonstrable experience of 10+ years in the Communications industry
Proficient in managing Cisco Routers
Expertise in Network Design
Proven skills in Network Engineering
Familiarity with Layer 3 Switches
Proficiency in working with Juniper Networks
Experience with Ribbon Fiber - Neptune

Job Responsibility

Lead the planning, design, engineering, testing, and implementation of a secure and robust converged voice, video, and data network infrastructure to support our operations
Collaborate with the CTO and Network/IT leadership for short and long-term planning of network and communication infrastructure, including operational improvements and best practices
Generate comprehensive "As Built" documents for the existing IP network, including all IP routers and switches, fiber network layout, lease circuits, and routing diagrams
Perform detailed IP routing and provisioning for various optical routers using equipment from vendors like Ribbon and Ekinops
Actively participate in field work, especially in the initial stages, followed by office-based responsibilities

What we offer

medical, vision, dental, and life and disability insurance
eligible to enroll in our company 401(k) plan

Fulltime

New

Senior Staff Silicon Design Engineer (Design Verification)

At AMD, our mission is to build great products that accelerate next-generation c...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in ASIC/SoC design
Strong hands-on verilog development experience, familiar with scripting languages like Perl
Good experience on complicate hub,control IP design
Strong problem solving, independent thinking, teamwork and communication skills
Bachelor or Master degree in E&E or Computer Engineering. (Preferred Master Degree)

Job Responsibility

Own part of IP feature design with cooperation with other designers
As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.

What we offer

AMD benefits at a glance.

Asic Physical Design Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

United States , San Jose

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

BS degree in electrical engineering
computer engineering
or a related field with 7+ years of experience in block or full-chip physical design
Deep design experience in large SoC designs
including IP integration
padring design
bump planning
and RDL routing strategy
Extensive knowledge and practices in Physical Design
including physically aware synthesis

Job Responsibility

Implement physical design at the large SoC chip level from RTL to GDSII
create a design database ready for manufacturing
Interact with IP vendors to understand IP integration requirements and integrate all blocks
IPs
and sub-chips at a large SoC level
Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement
Build full chip floorplan
including pads/ports/bump placement
block placement and optimization
block pins placement and alignment

What we offer

Comprehensive suite of benefits that supports physical
financial and emotional wellbeing
Personal and professional development programs
Unconditional inclusion and flexibility to manage work and personal needs

Fulltime

Silicon Design Engineer

Be part of AMD IO IP team, joining IP design work on host controller IP for the ...

Location

Taiwan , Hsinchu; Taipei

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Expert in Static Timing Analysis, familiar with DC, PT, GCA, and commands, worked in timing closure tasks with high clock frequency
Expert in Verilog RTL design on large-scale digital IP
Good English communication, presentation, and documentation
Work is performed with limited supervision. Strong sense of task scheduling and delivering on time as predetermined milestones committed to the manager
Can solve complex, novel, and non-recurring problems
Major in EE, CS or related, Master Degree or Bachelor with solid working experiences

Job Responsibility

Takes part in host controller development based on architectural requirements for next-generation IO
Works on STA tasks such as defining clock architecture, creating SDC and exceptions, and analyzing timing reports
Works on RTL code development for IP blocks in Verilog HDL to ensure functionality is correct and reusable for multiple product lines
Deals with complex problems in both STA and RTL
Makes technical decisions
Coaches and mentors junior staff

Principal IP Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Job Responsibility

Contribute to Security IP Roadmap Design: translate system/security architecture goals into project plans, milestones, and deliverables across multiple IP blocks/subsystems.
Hands-on Design Lead: Design leads for large subsystems or complex IP cores.
Drive end-to-end delivery of Security IP RTL and integration: oversee micro-architecture → RTL implementation → FE customer integration program needs (schedule + quality)
Enforce design quality and signoff rigor: define/optimize processes, best practices, and quality checks (e.g., lint/CDC/RDC-style hygiene, release criteria) to achieve “first-time-right” outcomes.
Embed “security as a product feature” into engineering execution: drive threat-informed design decisions, security posture accountability, and crisp communication of risks/priorities to stakeholders and leadership.
Predictable Execution: Track execution using ADO Tasks and ensure we are on track vs the plan.
Customer Obsessed: Partner with customers to ensure clean collaboration and feedback informing design execution, ensuring highest possible customer satisfaction.

Fulltime

Principal Engineer, VLSI Design Engineering

Sandisk understands how people and businesses consume data and we relentlessly i...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelors/ Masters degree in Electrical/ Electronics Engineering with 8+ years of experience in Analog Circuit Design across different technologies
Experience in developing analog IPs like Switch capacitor circuits, LDO, DC-DC convertor, oscillator, ADCs
Experience in integrating Analog IPs in a complex system
Knowledge of PCB and system design will be preferred
Experience in silicon characterization and probing
Experience in a multi-site environment, interacting with teams in other sites
Possess good mentorship skills
Ability to coordinate priorities and initiatives

Job Responsibility

Work in collaboration with global design teams across sites
Drive innovation in Analog IP designs
Design of IPs like Switched capacitor circuits, Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools
Provide technical leadership and mentor junior engineers
Develop processes and robust design methodology
Help build overall competency in Analog domain

Fulltime

Senior Manager Silicon Design Engineer

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

12-15 years full-time experience in IP hardware design
Proven experience managing and leading engineering teams
Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
Clock domain crossing (CDC) tools
Detailed understanding of SoC design flows
Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating
Outstanding interaction skills while communicating both written and verbally
Ability to work with multi-level functional teams across various geographies
Outstanding problem-solving and analytical skills

Job Responsibility

Lead a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies
Help bring to life cutting-edge designs, working closely with architecture, physical design, and product engineers to achieve first pass silicon success
Design of IP and subsystems with integration of AMD and other 3rd party IPs
Work collaboratively with other members of the IP team to support design verification, implementation, synthesis, constraints, static timing analysis, and delivery to SOC
Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up

IP Designer

IGG Canada

Location:
Indonesia , Jakarta

Category:
Art and Entertainment

Contract Type:
Not provided

Salary:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
March 01, 2026

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Location:Indonesia , Jakarta

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Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:March 01, 2026

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