CrawlJobs Logo

Interconnect System Architect

United States, Mountain View 163000.00 - 296400.00 USD / Year · Job Posted January 30, 2026
Apply Position
Job Link Share

Job Description

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Hardware Systems Engineering (CHSE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for an Interconnect System Architect to join the System Design team. The Interconnect System Architect drives co-design efforts between silicon and system teams, integrating cutting-edge interconnect technologies. This role is pivotal for next-generation high-speed connectivity solutions across Microsoft hardware platforms. The ideal candidate will have demonstrated significant experience in high speed system design with advanced interconnectivity technologies. Our team is at the forefront of technology and system design, leading the way for the next generation of platforms. Our mission is to architect the most performant, secure, reliable, and cost-effective solutions that are deployed at hyperscale to power Azure. The architect filling this role will be the subject matter expert to address the interconnectivity challenge in the silicon package, in the module, in the tray, in the rack and in the cluster. The architect will collaborate with the Planning and Sourcing teams and with Mechanical and Thermal Architects on requirements capture, technology insertion, concept proposals, cost/performance tradeoffs, prototype engineering, and architectural documentation for design/planning reviews. Once a program is approved from a conceptual level, the Architect will partner with the development teams to ensure a smooth transition to full product development. This individual will also champion innovative technical principles, design strategy and forward-looking technologies related to industry trends, drive the codesign with the full hardware stack from silicon to node, rack and cluster. Helping articulate and define our next generation interconnectivity technology. Come join this exciting and growing team through our monumental evolution of cloud hardware at Azure and Microsoft!

Job Responsibility

  • Lead silicon–system co‑design for high‑speed electrical and optical interconnects (die‑to‑die, package, board, cable/backplane), ensuring coherent requirements flow between SoC/ASIC, packaging, module, and system architectures.
  • Drive the interconnect technology roadmap, define inflection points, readiness criteria, and insertion plans across near‑, mid‑, and long‑term horizons
  • drive make/buy/partner decisions with clear TCO, risk, and schedule tradeoffs.
  • Drive end‑to‑end SI/PI performance, spanning package→module→tray→rack→cluster to deliver scalable bandwidth density, latency, power, and reliability targets. Work with SI team to establish channel budgets
  • guide stack‑ups, materials, connector/cable selections
  • standardize modeling, simulation, and validation methodologies for BER/jitter, crosstalk, S‑parameters, and compliance.
  • Represent Microsoft at industry conferences/consortia and in standards efforts (OIF, IEEE, OCP, OFC, etc.), publish/present to advance ecosystem alignment.
  • Influence roadmaps with PHY, connector, substrate, PCB, cable, and optical vendors
  • evaluate emerging technologies
  • incubate POCs that de‑risk insertion into program plans.

Requirements

  • Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 9+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 11+ years technical engineering experience
  • OR equivalent experience.
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Nice to have

  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • 15+ years in interconnect/system architecture, SI/PI, and high‑speed link design for large‑scale systems (servers, accelerators, networking, or comparable).
  • Proven silicon–package–board co‑design experience: channel definition, PHY requirements, equalization/FFE/DFE tradeoffs, retimer/redriver choices, and end‑to‑end closure.
  • Hands‑on modeling & simulation (e.g., IBIS‑AMI/Statistical/Time‑Domain, S‑parameter manipulation, eye/jitter analysis) and relevant EDA/EM tools (e.g., HFSS, Clarity/Siemens/Ansys, ADS, Sigrity, HSPICE/PrimeSim, MATLAB/Python).
  • Demonstrated cross‑functional leadership and communication skills—able to drive architecture decisions and tradeoffs with senior technical leaders.
  • Proven analytical and problem-solving skills with a focus on performance optimization.
  • Proven intellectual curiosity and a passion for challenging the status quo and driving disruptive innovation
  • PhD in EE/CE/Physics (or equivalent).
  • Expertise with PCIe Gen6/Gen7 (PAM4), Ethernet 112G/224G PAM4, UCIe/XSR/USR links, retimer/redriver, CPC and CPO considerations.
  • Experience with advanced packaging (2.5D/3D, HBM, organic/ABF, glass/interposers), substrate design rules, and warpage/thermo‑mechanical interactions.
  • System‑level architecture across node/rack/cluster, including thermal‑mechanical constraints, serviceability, and manufacturability at cloud scale.
  • Track record of public technical contributions (e.g., DesignCon/Hot Interconnects/OFCS papers, standards proposals), patents, or open‑source/consortia leadership.
  • Deep insight in global supply chain dynamics and technology trends

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Similar Jobs for

Interconnect System Architect

8 matching positions

System Architect, Distinguished Technologist, HPC & AI

Strong solution level understanding of high performance, liquid cooled, HPC and ...
Location
Location
United States , Houston
Salary
Salary:
161000.00 - 389500.00 USD / Year
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's, Master's or PhD degree in Electrical Engineering
  • Typically 10+ years experience
  • Industry expert regarding development of electronic hardware
  • Experience with HPC and AI systems
  • Experience with high speed interconnects that support HPC and AI systems (Infiniband, Cray Slingshot, Ethernet)
  • Familiarity with the SW used on HPC and AI systems (schedulers, MPI SW, etc.)
  • Familiarity with AMD and Nvidia architectures, including their SW stacks (ROCM and CUDA)
  • History of innovation with multiple patents in the field of electronics and hardware design
  • Outstanding analytical and problem solving skills
  • Experience in overall architecture of electronic hardware for products and solutions
Job Responsibility
Job Responsibility
  • Develops strategy and technology roadmaps for electrical hardware design and development engineering across the Global Business Unit and company at large
  • Work with customers and HPE solution architects to develop bid responses and architectural proposals to support those bids and also be the interface back to the engineering teams that are developing the platforms to provide appropriate guidance
  • Provides consultation, design input, and feedback for new product development and design reviews across multiple organizations and architectures
  • Guides and mentors less-experienced staff members to set an example of electrical hardware design and development innovation and excellence
  • Participates in and provides input on process for selection of future technical leaders
What we offer
What we offer
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
  • Fulltime
Read More
Arrow Right

Senior Principal AI Interconnect Architect

An AI Interconnect Architect defines and engineers high-speed networking and com...
Location
Location
United States , Milpitas
Salary
Salary:
194425.00 - 322092.00 USD / Year
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
  • 10 - 15 years experience developing interconnect technologies including transport and link level protocols, switching fabrics, QoS and reliable communication methods, and Software Defined Networking
  • Familiarity with various fabric topologies such as Fat tree, Leaf-Spine (Clos), Torus, Meshed and their applicability to various workload and system configurations
  • Familiarity with GPU/accelerator clusters and data center infrastructure
  • Deep, working knowledge of various interconnect technologies and protocols such as PCIe, CXL, NVLink, UALink, Ethernet, Ultra-Ethernet, and serial links
  • Ability to develop performance models
Job Responsibility
Job Responsibility
  • Develop architectures for chip-to-chip interconnects and switched fabrics tailored for AI/ML scale-out
  • Analyze trade-offs in bandwidth, latency, power, area, and reliability
  • Participate in industry standard bodies and contribute/influence/shape the direction of industry specifications
  • Work with SoC, package design, and software teams to ensure seamless integration
What we offer
What we offer
  • paid vacation time
  • paid sick leave
  • medical/dental/vision insurance
  • life, accident and disability insurance
  • tax-advantaged flexible spending and health savings accounts
  • employee assistance program
  • other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
  • tuition reimbursement
  • transit
  • the Applause Program
  • Fulltime
Read More
Arrow Right

System Architect

We are looking for a System Architect to support complex modeling, architecture,...
Location
Location
United States , Dayton
Salary
Salary:
Not provided
https://www.roberthalf.com Logo
Robert Half
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's degree in Systems Engineering, Aerospace Engineering, or a related technical discipline
  • At least 3 years of experience in systems engineering, architecture, or model-based engineering environments
  • Demonstrated knowledge of SysML and model-based systems engineering principles
  • Hands-on experience with tools such as MagicDraw, Cameo Systems Modeler, Rhapsody, Enterprise Architect, or comparable platforms
  • Ability to create, manage, and refine engineering models and associated technical data for complex systems
  • Strong written and verbal communication skills, including the ability to produce technical documentation and present findings clearly
  • Experience working effectively with cross-functional teams in a collaborative technical setting
  • Active Top Secret security clearance or the ability to obtain one
Job Responsibility
Job Responsibility
  • Build and update system architecture models, engineering artifacts, and structured technical representations for sophisticated platforms and interconnected systems
  • Apply SysML and model-based engineering tools to capture system behavior, interfaces, requirements, and design relationships
  • Work closely with engineers, developers, analysts, external partners, and government representatives to align technical models with program objectives
  • Prepare architecture documentation, briefings, and model-driven deliverables that support reviews, planning, and decision-making
  • Evaluate engineering data and architectural information to identify issues, recommend improvements, and strengthen technical approaches
  • Contribute to modeling, simulation, and analytical activities that support aerospace, defense, and national security initiatives
  • Maintain consistency and quality across model artifacts, ensuring traceability and usability for multidisciplinary teams
What we offer
What we offer
  • Medical
  • Vision
  • Dental
  • Life and disability insurance
  • 401(k) plan
  • Fulltime
Read More
Arrow Right

System Architect - BSP

Wind River is seeking an experienced developer to join the Helix Virtualization ...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
aptiv.com Logo
Aptiv plc
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BTech/MTech in Computer Science, Electrical/Computer Engineering, or equivalent
  • 14+ years experience in embedded software development, including BSP, HAL, bootloader, and device driver architecture
  • Strong knowledge of: Armv7/Armv8-A, Intel x86/64, or PowerPC architecture
  • MMU, cache, interrupt handling, SMP/AMP, timers, DMA, secure boot
  • Hardware virtualization mechanisms (Arm VE, VT-x, IOMMU, SMMU)
  • Proven experience with RTOS or hypervisor-based systems (VxWorks, QNX, HVP, Linux, FreeRTOS)
  • Strong proficiency in C and low-level debugging using JTAG, Lauterbach, and hardware probes
Job Responsibility
Job Responsibility
  • Define the architecture, design patterns, and standards for BSPs, HAL, bootloaders, and low‑level drivers for VxWorks and HVP
  • Create scalable, reusable BSP frameworks supporting heterogeneous SoCs and multi-core architectures
  • Guide the integration of virtualization technologies, partitioning, and safety‑critical design into BSP components
  • Lead system-level bring-up on Arm/Intel/PowerPC SoCs including MMU, cache, virtualization extensions, interrupt controllers, timers, security engines, and SoC interconnects
  • Architect and review drivers for high-speed peripherals: PCIe, Ethernet, USB, GPIO, DMA, UART, storage (eMMC/SD), and other SoC IPs
  • Ensure BSP designs meet performance, determinism, and safety (DO‑178C, IEC 61508, ISO 26262) requirements
  • Work with product management and system architects to define roadmaps and translate customer needs into deliverable architectures
  • Guide global engineering teams in implementation, reviews, optimization, and debugging
  • Support customer engagements as a technical authority for complex architectural decisions
  • Drive improvements in BSP development processes, coding guidelines (MISRA/CERT), certification readiness, and CI/CD pipeline adoption
  • Fulltime
Read More
Arrow Right

System Architect SME

As a leader in systems engineering, we’re looking for you to solve complex chall...
Location
Location
United States , Fayetteville
Salary
Salary:
99000.00 - 225000.00 USD / Year
boozallen.com Logo
Booz Allen Hamilton
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 5+ years of experience with Cisco UCS chassis, including blade servers and integrated components to support enterprise workloads and implementing service profiles in UCS Manager to streamline server provisioning, enforce consistency, and reduce deployment time
  • 5+ years of experience with configuring Fabric Interconnects for centralized management and unified fabric networking
  • 5+ years of experience with Server Management, and utilizing VMware, vSphere 7 or 8, Active Directory Domain Services, and Group Policy
  • 5+ years of experience managing Windows, including server setup, deployment, and maintenance, and troubleshooting networks
  • 3+ years of experience designing Server Rooms, including servers and networking, and NetAPP ONTAP
  • Experience with cloud-based technology
  • Experience with Python and PowerShell scripting
  • TS/SCI clearance
  • Bachelor’s degree
  • Security+ Certification
Job Responsibility
Job Responsibility
  • Combine technical skills with big picture thinking to make an impact in national security interests that directly support the Department of War
  • Understand your customer’s environment and how to develop the right systems for their mission
  • Translate real-world needs into technical specifications
  • Solve complex challenges and shape our client's mission requirements by leading engineering
  • Design and develop these systems and also evolve them with advanced technology solutions
  • Share your expertise through leadership and mentoring, while broadening your skillset into areas like Zero Trust and Cloud Technologies
What we offer
What we offer
  • Health, life, disability, financial, and retirement benefits
  • Paid leave
  • Professional development
  • Tuition assistance
  • Work-life programs
  • Dependent care
  • Recognition awards program
Read More
Arrow Right

AI System Security Architect

We are seeking a hands-on systemic & results-oriented System Security Architect/...
Location
Location
United States , Austin
Salary
Salary:
204000.00 - 306000.00 USD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Expert knowledge of a broad spectrum of datacenter security technologies including secure boot, secure update, attestation, confidential compute, and trusted execution environment (TEE) architecture
  • Well versed in relevant industry standards in these areas
  • Deep experience in designing and deploying production quality security solutions
  • Expertise in trusted execution environment (TEE) architecture of datacenter security technologies
  • Experience in designing and deploying production-grade security solutions and protocols
  • Good knowledge of security and cryptography principles, standards, and algorithms
  • Familiarity with datacenter systems management technologies and its components
  • Strong knowledge of embedded interconnect technologies, such as I2C/I3C, SPI, USB, PCIe etc
  • Ability to read and interpret board schematics and data sheets
  • Proficiency in programming/scripting languages, such as C/C++, Python, or other HW development languages
Job Responsibility
Job Responsibility
  • Define pragmatic and usable system security solutions across the datacenter hardware, firmware, and software stack
  • Work closely with multiple technical teams to drive and support the implementation, validation, and deployment of system security solutions
  • Hands-on collaboration with diverse teams to evaluate and develop innovative security solutions and proof of concept
  • Define and drive deployment of industry security best practices across diverse teams and technologies
  • Threat modelling and security issue analysis across hardware, firmware, and software
What we offer
What we offer
  • Benefits offered are described: AMD benefits at a glance
  • Fulltime
Read More
Arrow Right

Fellow - FPGA architecture

We are seeking a Fellow Architect to define and drive next‑generation architectu...
Location
Location
United States , San Jose
Salary
Salary:
268320.00 - 402480.00 USD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Strong Expertise in FPGA configuration, Partial Reconfiguration, and bitstream architecture
  • Experience with readback/debug infrastructure and field diagnostics
  • Background in ASIC/SoC design flows
  • Familiarity with FPGA toolchains (synthesis, P&R, PR flows)
  • Ability to define architecture across silicon, tools, and software layers
  • BS, MS, or PhD in Electrical/Computer Engineering or related field
  • Recognized technical leader in FPGA systems or architecture with significant architectural contributions, patents, publications, or industry impact
Job Responsibility
Job Responsibility
  • Own FPGA configuration architecture, including bitstream, boot flows, interfaces, compression, security, and reliability
  • Define next‑generation Partial Reconfiguration architecture for low‑latency, secure dynamic updates
  • Drive innovation in runtime reconfiguration for high‑availability and adaptive systems
  • Architect readback, debug, and observability infrastructure for validation and in‑field diagnostics
  • Define configuration security, including secure boot, key management, and update flows
  • Drive system trade-offs across configuration bandwidth, latency, and power, including memory and interconnect interactions
  • Develop clear architecture specifications for configuration, PR, and debug subsystems
  • Align with software/tools teams for end‑to‑end configuration and PR flows
  • Collaborate with silicon and design teams for scalable high‑quality implementation
  • Influence product roadmap and customer engagement for PR‑driven solutions
What we offer
What we offer
  • Benefits offered are described: AMD benefits at a glance.
  • Fulltime
Read More
Arrow Right

Public Cloud Network Lead

Join us at Barclays as a Public Cloud Network Lead, to architect, implement and ...
Location
Location
United Kingdom , London; Glasgow
Salary
Salary:
Not provided
barclays.co.uk Logo
Barclays
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Multi-Cloud Network Architecture & Hybrid Connectivity – Lead enterprise-scale network design across AWS, Azure, and GCP, delivering hybrid connectivity, encrypted interconnects (MACsec/IPsec), circuit provider management, and legacy infrastructure remediation through Infrastructure as Code
  • Network Security & Compliance – Implement Zero Trust segmentation, deploy cloud-native firewall controls, and ensure compliance with PCI-DSS, DORA, and internal governance frameworks
  • Strategic Planning, Consultancy & Stakeholder Engagement – Define cloud network strategy, evaluate emerging technologies, produce ADRs and HLD/LLD designs, lead Landing Zone design, and influence senior stakeholders on risk, strategy, and cost optimisation
  • Operational Excellence & Incident Response – Own incident escalation, SLA/SLO monitoring, flow analysis, and SRE enablement to drive network operational excellence
  • Automation, IaC & DevOps Practices – Build reusable Terraform, CloudFormation, and Bicep IaC with CI/CD pipelines and Python/Bash automation for standardised network provisioning
Job Responsibility
Job Responsibility
  • architect, implement and operate enterprise-grade multi-cloud network infrastructure at scale for Barclays
  • design secure, high-performance hybrid and multi-cloud architectures connecting thousands of cloud accounts across global regions to Barclays' on-premises infrastructure
  • work horizontally across GTIS Networks, SRE, DevOps, Product, and senior leadership to deliver strategic initiatives and resolve complex technical debt
  • mentor engineers and serving as the escalation point for critical network incidents
  • Build Engineering: Development, delivery, and maintenance of high-quality infrastructure solutions to fulfil business requirements
  • Incident Management: Monitoring of IT infrastructure and system performance to measure, identify, address, and resolve any potential issues, vulnerabilities, or outages
  • Automation: Development and implementation of automated tasks and processes to improve efficiency and reduce manual intervention
  • Security: Implementation of a secure configuration and measures to protect infrastructure against cyber-attacks, vulnerabilities, and other security threats
  • Teamwork: Cross-functional collaboration with product managers, architects, and other engineers to define IT Infrastructure requirements, devise solutions, and ensure seamless integration and alignment with business objectives
  • Learning: Stay informed of industry technology trends and innovations, and actively contribute to the organization's technology communities to foster a culture of technical excellence and growth
What we offer
What we offer
  • Competitive holiday allowance
  • Life assurance
  • Private medical care
  • Pension contribution
  • Fulltime
Read More
Arrow Right