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The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Job Responsibility:
Lead complex package design programs, planning and driving schedules from concept through implementation and tapeout
Optimize package pinouts, stack-ups, power distribution, and high-speed routing, balancing performance, manufacturability, and reliability
Collaborate with silicon floor planning, signal integrity (SI), and power integrity (PI) teams to ensure design quality and system-level alignment
Work closely with layout editors and implementation teams to deliver high-quality package layouts aligned with interface and manufacturing requirements
Serve as the technical and organizational leader of the San Jose package design team, providing direction, mentorship, and technical guidance to engineers
Develop and grow package design capability within the team, mentoring engineers and enabling them to take ownership of increasingly complex package programs
Coordinate resources across designers, layout editors, and contractors to support efficient project execution
Enhance package design methodologies and partner with vendors to improve product quality and efficiency
Drive innovation in package solutions for Cisco’s next-generation ASIC platforms
Requirements:
Bachelor’s degree in electrical engineering or a related field with 12+ years of work experience or Master’s degree in Electrical Engineering or a related field with 8+ years of work experience
Experience in high-speed package design, including signal integrity considerations and power distribution networks (PDN)
Experience with industry-standard EDA tools for package layout and design
Experience with technical leadership in complex hardware or silicon development programs
Nice to have:
Extensive experience in ASIC package design, including pinout optimization and high-speed routing
Knowledge of silicon floor planning and strong collaboration with SI and PI teams
Experience leading or mentoring engineering teams and developing technical talent
Experience coordinating complex cross-functional hardware development programs
Experience with testing and measurement equipment (oscilloscopes, TDR/VNA analyzers)
Experience with scripting languages such as Python, Perl, TCL, or shell programming
What we offer:
medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer