IC Package design engineer Job at Duo Security (Bangalore)

Analog/Mixed-Signal IC Design Director

SCALINX is seeking a highly influential Analog/Mixed-Signal IC design team leade...

Location

France , Paris/Caen/Grenoble

Salary:

Not provided

SCALINX

Expiration Date

Until further notice

Requirements

Proven industrial experience in: Architecture/design & validation of high-speed Nyquist-Rate data converters IP blocks (time-interleaved pipeline/SAR ADC architecture & current-steering DAC architectures)
Architecture/design of calibration circuits enhancing data converters performance
Integration of high-speed data converters IP blocks in complex mostly digital SoC (with strong knowledge of mixed-signals verification strategies/tools, signal integrity/power integrity & crosstalk issues)
Strong understanding of clocking circuit concepts and design trade-off to implement high-performance, high-speed data converters
Expert in AMS design/layout methodology
Experience in supervising mixed-signals designers and able to dive into technical details (down to transistor level)
Work across teams: Strong ability to resolve complex cross-functional issues
Design experience in advanced CMOS process
Excellent verbal and written communication (English required)
15+ years of experience in IC design and technical leadership

Job Responsibility

Manage a team of ~25 people including architects and AMS design/layout engineers in the field of deep sub-micron technology SoCs
Lead all aspects of design from concept to production, including architecture, specifications, transistor-level design, modelling, verification, layout, post-silicon validation support, productization support, etc.
Lead cross-functionally to ensure program cohesion with teams such as marketing, systems design, digital front-end/back-end teams, validation, productization, quality, applications, packaging, etc.
Ensure quality and reliability standards are met for volume production
Develop methodology and processes for “first time right” products
Participate in communication with high-profile customers
Actively participate in the technology roadmap definition
Report development progress to executive management

Fulltime

Senior IC Packaging Engineer

The Senior IC Package Engineer will be responsible for providing expertise, insi...

Location

United States , Hillsboro

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, Physics, Chemistry or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Chemistry or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Chemistry or related field AND 5+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
This role will require access to information that is controlled for export under export control regulations.
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status.

Job Responsibility

Work with product architects to determine the optimal packaging solution
Drive package technology solutions for chiplet architecture with advanced packaging.
Drive supplier assessments and manage suppliers through definition, development, qualification and production.
Develop and deliver FMEA (Failure Mode and Effects Analysis) for various technology options.
Define, design and develop test vehicles to validate Silicon, Package, System performance.
Support substrate design working with suppliers and internal teams
Assess and characterize the reliability of Integrated Circuits (IC) packages.
Design and develop package and assembly drawings to support the manufacturing.
Work closely with silicon and platform architects, motherboard and package designers, thermal architects and engineers, and power and performance engineers.
Drives the execution of architecture solutions across product lines or multiple product groups and across teams that account for design trends and future concepts by leveraging cross- functional expertise, industry best practices, and lessons learned from teams working across multiple product lines.

Fulltime

Substrate IC Package Layout Design Engineer

As a Substrate IC Package Layout Design Engineer you will be responsible for the...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
10+ years of experience in IC substrate layout design for high-performance processors or accelerators
Extensive experience with large substrate packages (>50mm) and complex high-density layouts
Proven experience with high-power (700W+) package designs and robust power delivery networks
Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches)
Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWos
Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification)
Deep understanding of SI/PI principles and how they apply to package-level design
Strong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment

Job Responsibility

IC Substrate Layout Design: Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators
Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements
Ensure robust power delivery designs capable of supporting >700W custom silicon solutions
High-Speed Signal Routing & Integrity: Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk
Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout
Advanced Packaging & CoWoS Integration: Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance
Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability
Design Validation & Verification: Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs
Develop and maintain design documentation and guidelines for future substrate designs
Support design reviews and provide technical guidance to junior team members

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

Manager, Process Module Engineering (Packaging Engineering)

To lead Die Attach Process Module Engineering team for Process/Materials Develop...

Location

Malaysia , Batu Kawan, Penang

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Master Degree or PhD in Materials Engineering / Mechanical Engineering / Physics / Micro-electronics
Strong hands-on experience Packaging technology development experience and well-versed with structured R&D methodology
Strong experience in driving technology roadmap and technology innovation to achieve best-in-class advanced packaging technology solutions
Minimum 10 years of Semiconductor Packaging Process with in-depth knowledge on IC packaging processes, high-density / ultra-thin die stacking technology development hands-on & indepth exposure
Proven capabilities to navigate through highly dynamic and fast-paced project requirements and interdependencies
Ability to lead complex technical investigation and analysis with global cross-functional teams
Ability to work with internal development / HVM teams and suppliers on process qualification and co-development

Job Responsibility

To lead Die Attach Process Module Engineering team for Process/Materials Development, Qualification and Transfer to HVM
Responsible for Key technology development & tech-staging to drive and enable product, process and materials technology roadmap solutions for next generation memory storage packaging solutions
To lead or co-lead Development JET (Joint Engineering Team) with global cross-functional teams incl. process, materials, CPI, package design, thermal-mechanical simulation, quality and other related stakeholders
To build and nurture strong process development team related to high density ultra-thin die attach process, material and packaging architecture - emphasizing deep engineering fundamental, structured methodology and DOE planning / execution / analysis
To lead studies related to in-depth fundamental investigation/characterization in packaging development
Ensure strong materials to process/design compatibility to meet stringent quality and reliability requirements from customers and industry standards
To co-drive material technology roadmap definition and path finding/development programs with global cross-functional teams including product design, process engineering, lab characterization teams and test engineering in delivering Best-In-Class and Industry leading products
To lead and drive collaboration with strategic equipment & material suppliers, service providers, academia, industry consortium in collaboration projects or co-development activities
To drive breakthrough in product packaging materials and process
To support IR5.0 Digital Transformation for Packaging process e.g. Process Digital Twins, Advanced Process Control (APC), Fault Detection Control (FDC), fundamental lab characterization and design rules definition

Fulltime

Senior Digital IC Design Engineer

SCALINX’s design team is seeking a dynamic and experienced digital designer who ...

Location

France , Paris; Caen; Grenoble

Salary:

Not provided

SCALINX

Expiration Date

Until further notice

Requirements

MSc or PhD in Electrical Engineering or equivalent
Very good understanding of the entire digital IC design flow from RTL to GDSII
Strong expertise in digital electronics and signal processing
Proven experience in digital IC projects and technical leadership roles
Strong experience with ARM or RISC-V based SoC platform design
Solid experience with high-speed serial interfaces (JESD204, Ethernet, PCIe…)
Expertise in digital hardware description languages (VHDL or Verilog) and SystemVerilog
Experience with Cadence, Synopsys or Siemens RTL design flow
Proven experience with GIT and Linux systems
Skilled in scripting languages (Python, TCL, Perl)

Job Responsibility

Design of complex RTL blocks based on micro-architecture specifications
Top level integration of various RTL blocks and complex IPs
Execute complete LINT/CDC/RDC checks
Write SDC constraints to run logical synthesis
Write detailed design documentation in accordance with company QA policy
Generates KPI and report progress to the Program Manager
Timely deliver state-of-the-art RTL package to Digital Verification, DFT and Back-End teams
Lead and support digital design work-packages from RTL to netlist
Animate design reviews
Participate with the other project technical leaders in the definition of the IC architecture specifications and verification methodology

Fulltime

Senior Digital IC Design Engineer

SCALINX’s design team is seeking a dynamic and experienced digital designer who ...

Location

France , Paris; Caen; Grenoble

Salary:

Not provided

SCALINX

Expiration Date

Until further notice

Requirements

MSc or PhD in Electrical Engineering or equivalent
Very good understanding of the entire digital IC design flow from RTL to GDSII
Strong expertise in digital electronics and signal processing
Proven experience in digital IC projects and technical leadership roles
Strong experience with ARM or RISC-V based SoC platform design
Solid experience with high-speed serial interfaces (JESD204, Ethernet, PCIe…)
Expertise in digital hardware description languages (VHDL or Verilog) and SystemVerilog
Experience with Cadence, Synopsys or Siemens RTL design flow
Proven experience with GIT and Linux systems
Skilled in scripting languages (Python, TCL, Perl)

Job Responsibility

Design of complex RTL blocks based on micro-architecture specifications
Top level integration of various RTL blocks and complex IPs
Execute complete LINT/CDC/RDC checks
Write SDC constraints to run logical synthesis
Write detailed design documentation in accordance with company QA policy
Generates KPI and report progress to the Program Manager
Timely deliver state-of-the-art RTL package to Digital Verification, DFT and Back-End teams
Lead and support digital design work-packages from RTL to netlist
Animate design reviews
Participate with the other project technical leaders in the definition of the IC architecture specifications and verification methodology

New

Research Assistant – Mixed signal IC and System Designer

Within the research area, RF and High-Speed Transceivers, applicant is sought fo...

Location

Ireland , Cork

Salary:

33791.00 - 43872.00 EUR / Year

Tyndall National Institute

Expiration Date

April 13, 2026

Requirements

A Bachelor(honours), Irish Masters or equivalent degree in Electrical / Electronics Engineering, Computer Science, Physics or in a related area, completed or close to completion
Strong background in digital IC design, including RTL design using VHDL/Verilog/SystemVerilog
Familiarity with FPGA development tools (Xilinx Vivado, Intel Quartus, or equivalent)
Experience with RF measurements and test instrumentation (VNAs, spectrum analyzers)
Familiarity with EDA tools (Cadence, Synopsys, Mentor Graphics) for digital design and verification
Good understanding of hardware bring-up and mixed-signal debugging
Strong programming skills in MATLAB, Python, or C/C++ for modeling and analysis
Ability to work in an interdisciplinary research environment with RF and mixed-signal teams
Excellent written and verbal communication skills in English

Job Responsibility

Develop FPGA-based control and data acquisition systems for RF and packaging test setups
Design and verify RTL modules (VHDL/Verilog) for real-time measurement and interface control
Support hardware validation, including S-parameter, signal integrity, and time-domain measurements
Develop and execute test plans for functional verification, timing validation, and power analysis
Contribute to the design, evaluation and testing of advanced packaging solutions (e.g., interposers, 3D integration, high-frequency interconnects) for mixed-signal and RF IC systems
Automate test and data acquisition using Python/LabVIEW/MATLAB scripts
Document and present test results, contributing to project reports and publications
Collaborate with RF designers, packaging engineers, and FPGA developers within MCCI and e-Perfect partners
Ensure compliance with Tyndall’s Quality Management Systems, Health and Safety standards, and other regulations
To carry out any additional duties that may reasonably be required within the general scope and level of the post

What we offer

Opportunities to contribute to ground-breaking research and innovation that shape Ireland’s economy and the society at large
Strong support for formal training, further study and professional development
Where academia, industry, and innovation intersect - supported by cutting-edge infrastructure and expert knowledge
Flexibility to work remotely and on-site, where the role allows
Access to UCC pension, long-term illness benefit, life assurance, and more
Competitive annual leave entitlements
Athena Swan Bronze award holder, with ongoing initiatives led by a dedicated People and Culture team to ensure equity for all
A culture grounded in Ambition, Collaboration, Diversity, Excellence, and Integrity
A proactive, innovation-driven environment that welcomes entrepreneurial and creative thinkers, including those with start-up experience
Structured induction and mentoring to help new hires integrate and thrive

Fulltime

!

Principal Signal Integrity Engineer

We are seeking a seasoned Signal and Power Integrity Engineer with expertise or ...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

MS or PhD in Electrical Engineering
Excellent analytical and problem-solving skills along with attention to details
Need a self-starter, someone able to drive tasks independently and efficiently to completion
Strong/effective communication skills
Enthusiastic team-first mentality
Experience with PCB, Package and IC level power delivery networks
Experience in silicon packaging and PCB design for signal and power integrity
Experience with high-speed digital signaling interfaces such as PCIE, GDDR6, HDMI
Expertise in electrical modeling EDA and AMS tools such as ADS, HFSS, SIwave, HSPICE
Expertise in electromagnetic theory and circuit analysis

Job Responsibility

Responsible for Signal Integrity and Power Integrity simulations at feasibility, pre-layout, post-layout phases of AECG characterization board and demo board design. Establish design and layout guidelines
Responsible for coordinating with HW design team, layout team, NPI and manufacturing vendors to resolve SI/PI related issues
Responsible for end-to-end channel simulations for multi gigabit serial lines like 56Gbps, 112Gbps and beyond
Responsible for PI analysis simulations of HBM/ /DDR4/LPDDR4/DDR5/LPDDR5 and other memory buses
Responsible for characterizing the various interfaces in the product and verifying the simulations against measurements
Responsible for preparation of and implementing checklists for various stages of PCB development
Worked with architecture team, package design team and PCB design team for future PCB technology
Update the SIPI design and analysis flow and automate the process

IC Package design engineer

Duo Security

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
February 19, 2026

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Job Description:

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