IC Package design engineer Job at Duo Security (Bangalore)

Substrate IC Package Layout Design Engineer

As a Substrate IC Package Layout Design Engineer you will be responsible for the...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
10+ years of experience in IC substrate layout design for high-performance processors or accelerators
Extensive experience with large substrate packages (>50mm) and complex high-density layouts
Proven experience with high-power (700W+) package designs and robust power delivery networks
Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches)
Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWos
Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification)
Deep understanding of SI/PI principles and how they apply to package-level design
Strong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment

Job Responsibility

IC Substrate Layout Design: Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators
Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements
Ensure robust power delivery designs capable of supporting >700W custom silicon solutions
High-Speed Signal Routing & Integrity: Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk
Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout
Advanced Packaging & CoWoS Integration: Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance
Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability
Design Validation & Verification: Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs
Develop and maintain design documentation and guidelines for future substrate designs
Support design reviews and provide technical guidance to junior team members

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

Senior Digital IC Design Engineer

SCALINX’s design team is seeking a dynamic and experienced digital designer who ...

Location

France , Paris; Caen; Grenoble

Salary:

Not provided

SCALINX

Expiration Date

Until further notice

Requirements

MSc or PhD in Electrical Engineering or equivalent
Very good understanding of the entire digital IC design flow from RTL to GDSII
Strong expertise in digital electronics and signal processing
Proven experience in digital IC projects and technical leadership roles
Strong experience with ARM or RISC-V based SoC platform design
Solid experience with high-speed serial interfaces (JESD204, Ethernet, PCIe…)
Expertise in digital hardware description languages (VHDL or Verilog) and SystemVerilog
Experience with Cadence, Synopsys or Siemens RTL design flow
Proven experience with GIT and Linux systems
Skilled in scripting languages (Python, TCL, Perl)

Job Responsibility

Design of complex RTL blocks based on micro-architecture specifications
Top level integration of various RTL blocks and complex IPs
Execute complete LINT/CDC/RDC checks
Write SDC constraints to run logical synthesis
Write detailed design documentation in accordance with company QA policy
Generates KPI and report progress to the Program Manager
Timely deliver state-of-the-art RTL package to Digital Verification, DFT and Back-End teams
Lead and support digital design work-packages from RTL to netlist
Animate design reviews
Participate with the other project technical leaders in the definition of the IC architecture specifications and verification methodology

Silicon Design Engineer

At AMD, our mission is to build great products that accelerate next-generation c...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong understanding of analog and/or digital IC design concepts
Familiarity with industry-standard EDA tools (Cadence Virtuoso, Synopsys, Mentor, etc.)
Experience or strong interest in scripting/programming (Python, SKILL, Tcl, or Perl)
Good problem-solving skills, attention to detail, and quality-focused mindset
Effective communication skills with a team-oriented and collaborative attitude
Positive, self-driven, and eager to learn in a fast-paced environment
Ability to work with global teams across multiple disciplines
Interest in automation, AI-assisted workflows, and next-generation engineering productivity solutions
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field

Job Responsibility

Develop, support, and maintain CAD design flows for schematic, layout, package, and physical verification
Define and deliver automation solutions to improve efficiency, quality, and turnaround time for design teams
Develop scripts, tools, and utilities (SKILL/Python/Tcl/Perl) for automation and workflow optimization
Support and enhance EDA tools and environments, including integration of in-house and vendor solutions
Work closely with design engineers to deploy, debug, and improve CAD flows
Assist in transforming existing engineering workflows into AI-assisted or agentic workflows, integrating intelligent automation to reduce manual effort and improve decision-making
Collaborate with global Mixed-Signal, CAD, and technology teams to address design and flow challenges

Mechanical Design Engineer

Imagine walking into a role where you aren't just tweaking old models or managin...

Location

United Kingdom , Peterborough

Salary:

33.50 - 35.50 GBP / Hour

Randstad

Expiration Date

July 15, 2026

Requirements

Proven Design Capability: Deep experience creating complex geometry using CAD software (CREO/Teamcenter preferred)
Sub-System Engine Knowledge: A strong grasp of rotating systems, bolted joints, and fluid systems (lubrication, cooling)
Internal Combustion Engines: A fundamental, robust understanding of IC engines (experience with highway/off-highway diesel or aerospace sectors is highly desirable)
Experience & Qualifications: Industry Specific: 3 to 5 years of dedicated design experience within relevant sectors (e.g., automotive, aerospace, off-highway)
Generalist: We will happily consider up to 10 years of broader mechanical design experience if you have strong transferable casting and machining knowledge
Education: A technical degree or HNC in mechanical/automotive engineering is preferred, though equivalent practical experience is highly valued
Strong technical writing and presentation skills
The ability to communicate confidently and collaborate effectively across global boundaries

Job Responsibility

Clean-Sheet Design: Design and package engine components (such as major aluminium/cast iron castings, geartrains, valvetrains, and in-cylinder components)
System Integration: Input into system design development for critical systems like breathing, cooling, FEAD, and lubrication
Lifecycle Ownership: Take your designs from concept to prototype and volume production, conducting design reviews and FMEAs to mitigate risks
Global Collaboration: Work closely with cross-functional global manufacturing sites, suppliers, and external partners using APQP methodologies

!

Senior Analog Design Engineer

We are the global test and automation specialists, powering next-generation tech...

Location

United States , Agoura Hills

Salary:

123100.00 - 193900.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

MSEE with 5 years of experience or PhD in electrical engineering with 3 years experience in the design and characterization of multiple, high frequency and high scale of integration mixed signal integrated circuits
Thorough knowledge of high frequency, broad-band Analog Mixed-Signal IC design – both electrical and physical design
Desire experience in design of VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high frequency I/Os, high frequency CML designs, high voltage, power circuits
Solid understanding of CMOS semiconductor device physics and device modeling
Solid understanding of electromagnetic theory
Solid understanding of transmission line theory
Solid understanding of thermal effects of various circuit topologies and different package types
Involvement in all phases of multiple IC developments from specification to product introduction
Solid understanding and experience with IC characterization at high frequencies using high speed sampling oscilloscopes, spectrum analyzers, VNAs, signal sources
Solid understanding of working with PDKs

Job Responsibility

Develop detailed circuit specifications for mixed signal circuits
Conceive circuit architectures and transistor level circuit topologies that satisfy required performance
Physical implementation (layout) of high speed circuits, either directly or assisting
Optimization of circuits via simulation (with Cadence EDA tools) over all process and operating conditions
Integration of circuit elements into large analog/mixed signals ASICs
Participation in the characterization of ASIC circuits

What we offer

medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs

Fulltime

Physical Design Engineer

In this role, you will be responsible for the implementation and signoff of comp...

Location

China , Beijing

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Full chip floorplan experience
Scripting language experience: Perl, Tcl, Python
Exposure to leadership or mentorship is an asset
Experience with high-performance CPU/GPU/AI accelerator physical design in advanced nodes (7nm and below)
Hands-on experience with low-power design techniques (power gating, multi-voltage, DVFS) and UPF/CPF flow
Familiarity with 3D-IC or chiplet-based design methodologies and associated tool flows
Knowledge of package-aware floorplanning and system-level co-design considerations
Experience with machine learning applications in physical design (e.g., auto-placement, routing prediction)
Prior exposure to design for testability (DFT) integration and post-silicon debug support
Proven track record of successful tape-outs in high-complexity SoC projects

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features
RTL-to-GDSII Implementation – Execute full physical design flow including synthesis, floorplanning, placement, CTS, routing, and signoff
Timing & Power Closure – Perform static timing analysis (STA), power analysis, and optimize designs to meet timing, power, and area goals
Physical Verification – Run DRC, LVS, and other verification checks to ensure design manufacturability
Methodology & Automation – Develop and maintain scripts to improve design efficiency and quality
Cross-functional Collaboration – Work with frontend, DFT, and CAD teams to resolve design issues and implement methodology improvements
Documentation & Reporting – Create clear documentation and regularly report progress to project stakeholders

Senior Analog Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , Hyderabad

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

MTech/MS with 2+ years or BTech/BS with 4+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field)
Proven expertise with FinFET technologies and CMOS tape-outs
Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures
Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC)
Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance
Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating)
Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators
Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results
Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk)
Excellent communication and documentation skills

Job Responsibility

Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications
Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed
Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality
Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance
Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews
Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements
Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Staff Analog Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , Hyderabad

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field)
Proven expertise with FinFET technologies and CMOS tape-outs
Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures
Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC)
Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance
Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating)
Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators
Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results
Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk)
Excellent communication and documentation skills

Job Responsibility

Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications
Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed
Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality
Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance
Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews
Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements
Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates

What we offer

Comprehensive medical and healthcare plans that work for you and your family
Time Away: In addition to company holidays, we have ETO and FTO Programs
Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans: Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

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IC Package design engineer

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