IC Package design engineer Job at Duo Security (Bangalore)

Analog/Mixed-Signal IC Design Director

SCALINX is seeking a highly influential Analog/Mixed-Signal IC design team leade...

Location

France , Paris/Caen/Grenoble

Salary:

Not provided

SCALINX

Expiration Date

Until further notice

Requirements

Proven industrial experience in: Architecture/design & validation of high-speed Nyquist-Rate data converters IP blocks (time-interleaved pipeline/SAR ADC architecture & current-steering DAC architectures)
Architecture/design of calibration circuits enhancing data converters performance
Integration of high-speed data converters IP blocks in complex mostly digital SoC (with strong knowledge of mixed-signals verification strategies/tools, signal integrity/power integrity & crosstalk issues)
Strong understanding of clocking circuit concepts and design trade-off to implement high-performance, high-speed data converters
Expert in AMS design/layout methodology
Experience in supervising mixed-signals designers and able to dive into technical details (down to transistor level)
Work across teams: Strong ability to resolve complex cross-functional issues
Design experience in advanced CMOS process
Excellent verbal and written communication (English required)
15+ years of experience in IC design and technical leadership

Job Responsibility

Manage a team of ~25 people including architects and AMS design/layout engineers in the field of deep sub-micron technology SoCs
Lead all aspects of design from concept to production, including architecture, specifications, transistor-level design, modelling, verification, layout, post-silicon validation support, productization support, etc.
Lead cross-functionally to ensure program cohesion with teams such as marketing, systems design, digital front-end/back-end teams, validation, productization, quality, applications, packaging, etc.
Ensure quality and reliability standards are met for volume production
Develop methodology and processes for “first time right” products
Participate in communication with high-profile customers
Actively participate in the technology roadmap definition
Report development progress to executive management

Fulltime

New

Substrate IC Package Layout Design Engineer

As a Substrate IC Package Layout Design Engineer you will be responsible for the...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
10+ years of experience in IC substrate layout design for high-performance processors or accelerators
Extensive experience with large substrate packages (>50mm) and complex high-density layouts
Proven experience with high-power (700W+) package designs and robust power delivery networks
Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches)
Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWos
Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification)
Deep understanding of SI/PI principles and how they apply to package-level design
Strong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment

Job Responsibility

IC Substrate Layout Design: Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators
Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements
Ensure robust power delivery designs capable of supporting >700W custom silicon solutions
High-Speed Signal Routing & Integrity: Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk
Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout
Advanced Packaging & CoWoS Integration: Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance
Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability
Design Validation & Verification: Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs
Develop and maintain design documentation and guidelines for future substrate designs
Support design reviews and provide technical guidance to junior team members

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

Manager, Process Module Engineering (Packaging Engineering)

To lead Die Attach Process Module Engineering team for Process/Materials Develop...

Location

Malaysia , Batu Kawan, Penang

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Master Degree or PhD in Materials Engineering / Mechanical Engineering / Physics / Micro-electronics
Strong hands-on experience Packaging technology development experience and well-versed with structured R&D methodology
Strong experience in driving technology roadmap and technology innovation to achieve best-in-class advanced packaging technology solutions
Minimum 10 years of Semiconductor Packaging Process with in-depth knowledge on IC packaging processes, high-density / ultra-thin die stacking technology development hands-on & indepth exposure
Proven capabilities to navigate through highly dynamic and fast-paced project requirements and interdependencies
Ability to lead complex technical investigation and analysis with global cross-functional teams
Ability to work with internal development / HVM teams and suppliers on process qualification and co-development

Job Responsibility

To lead Die Attach Process Module Engineering team for Process/Materials Development, Qualification and Transfer to HVM
Responsible for Key technology development & tech-staging to drive and enable product, process and materials technology roadmap solutions for next generation memory storage packaging solutions
To lead or co-lead Development JET (Joint Engineering Team) with global cross-functional teams incl. process, materials, CPI, package design, thermal-mechanical simulation, quality and other related stakeholders
To build and nurture strong process development team related to high density ultra-thin die attach process, material and packaging architecture - emphasizing deep engineering fundamental, structured methodology and DOE planning / execution / analysis
To lead studies related to in-depth fundamental investigation/characterization in packaging development
Ensure strong materials to process/design compatibility to meet stringent quality and reliability requirements from customers and industry standards
To co-drive material technology roadmap definition and path finding/development programs with global cross-functional teams including product design, process engineering, lab characterization teams and test engineering in delivering Best-In-Class and Industry leading products
To lead and drive collaboration with strategic equipment & material suppliers, service providers, academia, industry consortium in collaboration projects or co-development activities
To drive breakthrough in product packaging materials and process
To support IR5.0 Digital Transformation for Packaging process e.g. Process Digital Twins, Advanced Process Control (APC), Fault Detection Control (FDC), fundamental lab characterization and design rules definition

Fulltime

New

Senior Digital IC Design Engineer

SCALINX’s design team is seeking a dynamic and experienced digital designer who ...

Location

France , Paris; Caen; Grenoble

Salary:

Not provided

SCALINX

Expiration Date

Until further notice

Requirements

MSc or PhD in Electrical Engineering or equivalent
Very good understanding of the entire digital IC design flow from RTL to GDSII
Strong expertise in digital electronics and signal processing
Proven experience in digital IC projects and technical leadership roles
Strong experience with ARM or RISC-V based SoC platform design
Solid experience with high-speed serial interfaces (JESD204, Ethernet, PCIe…)
Expertise in digital hardware description languages (VHDL or Verilog) and SystemVerilog
Experience with Cadence, Synopsys or Siemens RTL design flow
Proven experience with GIT and Linux systems
Skilled in scripting languages (Python, TCL, Perl)

Job Responsibility

Design of complex RTL blocks based on micro-architecture specifications
Top level integration of various RTL blocks and complex IPs
Execute complete LINT/CDC/RDC checks
Write SDC constraints to run logical synthesis
Write detailed design documentation in accordance with company QA policy
Generates KPI and report progress to the Program Manager
Timely deliver state-of-the-art RTL package to Digital Verification, DFT and Back-End teams
Lead and support digital design work-packages from RTL to netlist
Animate design reviews
Participate with the other project technical leaders in the definition of the IC architecture specifications and verification methodology

Fulltime

New

Senior Digital IC Design Engineer

SCALINX’s design team is seeking a dynamic and experienced digital designer who ...

Location

France , Paris; Caen; Grenoble

Salary:

Not provided

SCALINX

Expiration Date

Until further notice

Requirements

MSc or PhD in Electrical Engineering or equivalent
Very good understanding of the entire digital IC design flow from RTL to GDSII
Strong expertise in digital electronics and signal processing
Proven experience in digital IC projects and technical leadership roles
Strong experience with ARM or RISC-V based SoC platform design
Solid experience with high-speed serial interfaces (JESD204, Ethernet, PCIe…)
Expertise in digital hardware description languages (VHDL or Verilog) and SystemVerilog
Experience with Cadence, Synopsys or Siemens RTL design flow
Proven experience with GIT and Linux systems
Skilled in scripting languages (Python, TCL, Perl)

Job Responsibility

Design of complex RTL blocks based on micro-architecture specifications
Top level integration of various RTL blocks and complex IPs
Execute complete LINT/CDC/RDC checks
Write SDC constraints to run logical synthesis
Write detailed design documentation in accordance with company QA policy
Generates KPI and report progress to the Program Manager
Timely deliver state-of-the-art RTL package to Digital Verification, DFT and Back-End teams
Lead and support digital design work-packages from RTL to netlist
Animate design reviews
Participate with the other project technical leaders in the definition of the IC architecture specifications and verification methodology

Senior Analog Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , Hyderabad

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

MTech/MS with 2+ years or BTech/BS with 4+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field)
Proven expertise with FinFET technologies and CMOS tape-outs
Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures
Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC)
Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance
Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating)
Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators
Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results
Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk)
Excellent communication and documentation skills

Job Responsibility

Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications
Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed
Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality
Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance
Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews
Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements
Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Staff Analog Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , Hyderabad

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field)
Proven expertise with FinFET technologies and CMOS tape-outs
Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures
Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC)
Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance
Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating)
Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators
Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results
Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk)
Excellent communication and documentation skills

Job Responsibility

Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications
Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed
Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality
Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance
Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews
Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements
Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates

What we offer

Comprehensive medical and healthcare plans that work for you and your family
Time Away: In addition to company holidays, we have ETO and FTO Programs
Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans: Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Senior Engineer, Packaging Engineering

Sandisk understands how people and businesses consume data and we relentlessly i...

Location

Malaysia , Batu Kawan, Penang

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor/Master/PhD engineering/material/science required
Minimum 5 years of relevant work experience (minimum 2 years for PhD)
Relevant work experience must be in engineering role within semiconductor industry
Academic studies must be in applicable field of engineering/science and demonstrate an academic record of excellence
Demonstrated track record to pathfinding and development new SMT material such as paste and epoxy with vendors and utilizing test methodology to qualify new material in factory
Demonstrated track record to rapidly analyze and solve complex engineering issues by pursuing a focused solution path with a clear understanding of technical fundamental on root causing thru failure analysis report (EDX/FTIR etc), simulation report, mechanical (shadow moire) analysis report, or any relevant metrology data collection
Demonstrated track record working hands-on around technical equipment and processes (including metrology and semiconductor failure analysis techniques)
Proficient in statistical analysis towards problem solving and the use of Minitab or JMP and Excel
Demonstrated track record to summarize complex data sets for technical and non-technical audiences
elegant in DOE design and execution

Job Responsibility

Defines IC package/SMT/SSD drive requirements, goals, and milestones for all SSD product groups and customer requirements
Develops SSD assembly and IC packaging material and processes to meet quality, reliability, cost, yield, productivity and manufacturing requirements
Develops new package and SMT process qualification programs
Prepares and/or updates specifications for piece parts of integrated circuits or semiconductor assemblies
Plans and conducts experiments to fully characterize material and processes throughout pathfinding to development to ramp
Develops solutions to improve quality, reliability, cost, yield, process stability/capability, productivity, and safety utilizing formal education, experience, statistical knowledge, and problem-solving tools
Establishes process control systems
Transfers process to high volume manufacturing and provide support in new factory start-up
Acts as a liaison with suppliers/vendors
Maintains product quality while developing and introducing package cost reduction programs

Fulltime

IC Package design engineer

Duo Security

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
February 19, 2026

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Job Description:

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Job Posted:February 19, 2026

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