Head of Design Verification, Interface IP

We are hiring a Head of Design Verification – Interface IP to own and scale verification for all major interface IP subsystems across Etched silicon. This is a hands-on technical leadership role: you will manage a small team while personally owning DV strategy, execution, and tape-out sign-off for critical subsystems including CPU subsystems, HBM memory controllers, PCIe, Ethernet, and system peripherals. You will lead Interface IP DV from architecture definition through tape-out, working closely with RTL designers, IP vendors, SoC and performance DV, software, and architecture teams. You will set standards, define best practices, and ensure verification quality scales with increasingly ambitious chips.