CrawlJobs Logo

Hardware Engineer - Core Compute

softworldinc.com Logo

Softworld

Location Icon

Location:
United States , Sterling Heights

Category Icon

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

50.00 - 65.00 USD / Hour

Job Description:

A leading U.S. defense contractor is seeking a Senior Electrical Hardware Engineer in Sterling Heights, MI to support the design, development, and qualification of ruggedized computing and interface hardware for ground combat vehicle systems. This is a contract-to-hire opportunity (12–36 months) focused on advanced processing, interface, and target detection hardware supporting Modular Open Systems Architecture (MOSA) and SOSA-aligned platforms. Compensation for this role ranges from $50–$65 per hour, based on experience and qualifications. This role offers the opportunity to work on mission-critical defense programs supporting next-generation ground vehicle technologies. The ideal candidate will contribute across the full hardware lifecycle—from requirements and architecture through design, debug, test, and qualification—while collaborating with cross-functional engineering teams in a hands-on, fast-paced environment. Engineers in this role gain exposure to cutting-edge open architecture standards, complex embedded systems, and long-term defense programs with strong stability and growth potential.

Job Responsibility:

  • Design and development of ruggedized computing and interface hardware for defense systems
  • Hardware architecture analysis, trade studies, and engineering reviews
  • Schematic development, component selection, circuit simulation, and PCB layout support
  • Embedded processor and microcontroller hardware design and integration
  • Hardware debug, test, qualification, and production support
  • Support for MOSA/SOSA-aligned system architectures and target detection applications
  • Collaborate with systems, software, and manufacturing teams to support end-to-end hardware development
  • Review and develop hardware and software requirements and associated test plans
  • Perform hands-on hardware debugging, validation, and design fixes
  • Maintain detailed documentation, revision tracking, and configuration control
  • Participate in technical reviews and provide engineering support throughout the product lifecycle

Requirements:

  • Bachelor’s degree in Electrical Engineering or Computer Engineering
  • 10+ years of experience designing, debugging, and testing electrical hardware for embedded or computing systems
  • Experience with ruggedized hardware designs supporting defense or mission-critical environments
  • Knowledge across multiple hardware domains including digital and analog circuit design, PCB layout, embedded microprocessor and microcontroller hardware design, and high-speed signal integrity
  • Familiarity with open architecture standards and technologies such as MOSA, SOSA, GCIA, and TSN
  • Experience working with industry-standard interfaces including PCIe, USB, RS-422/485, MIL-1553, Ethernet, and CAN
  • Strong written and verbal communication skills and ability to collaborate with multidisciplinary engineering teams
  • Ability to obtain a U.S. security clearance

Nice to have:

  • Target Detection hardware experience
  • FPGA design and simulation experience using Xilinx toolsets
  • Experience with graphics, video, and display interfaces
  • Familiarity with military design and test standards including MIL-1275, MIL-461, MIL-464, and MIL-810
  • Previous experience supporting ground combat vehicle programs
What we offer:
  • voluntary benefit plans including medical, dental, vision, telemedicine, term life, whole life, accident insurance, critical illness, a legal plan, and short-term disability
  • access to a retirement savings plan, service bonus and holiday pay plans (earn up to eight paid holidays per benefit year), and a transit spending account
  • earn paid sick leave under the applicable state or local plan

Additional Information:

Job Posted:
January 29, 2026

Employment Type:
Fulltime
Work Type:
On-site work
Job Link Share:

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Hardware Engineer - Core Compute

Senior Product Manager, Access Control Core Hardware and Fleet Management

This role is a key player in unlocking $7+ billion in Total Addressable Market (...
Location
Location
United States , San Mateo
Salary
Salary:
185000.00 - 215000.00 USD / Year
verkada.com Logo
Verkada
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 4-8+ years of high-impact Product Management experience
  • Direct experience managing physical hardware products, especially those involving electrical components, firmware, or IoT/connected devices
  • An undergraduate degree in Computer Science, Electrical Engineering, or a related engineering field
  • A mindset ready to dive into technical details, data, and technology to uncover insights
  • The ability to effectively bridge complex technical topics with business strategy
  • Proven track record supporting enterprise sales cycles and engaging effectively with large, complex customers
Job Responsibility
Job Responsibility
  • Own the full strategy, roadmap, and flawless execution for our core Access Control hardware portfolio, managing a complex fleet of devices from launch to scale
  • Own the portfolio of Access Controllers
  • Own the portfolio of wired Readers
  • Own state-of-the-art accessories, including next-gen battery tech
  • End-to-end responsibility for the fleet management software and strategies for management of these critical devices at scale
  • Deeply immerse yourself in the needs of critical, high-growth segments (Federal, Healthcare, Manufacturing, K-12) to identify opportunities
  • Partner with Product Marketing and Sales to craft compelling GTM strategies and messaging
  • Serve as the passionate voice of our customers, guiding product strategy
What we offer
What we offer
  • Healthcare programs with premiums 100% covered for the employee under at least one plan and 80% for family premiums
  • Nationwide medical, vision and dental coverage
  • Health Saving Account (HSA) with annual employer contributions
  • Flexible Spending Account (FSA) with tax saving options
  • Expanded mental health support
  • Paid parental leave policy & fertility benefits
  • Paid holidays, firmwide extended holidays, flexible PTO and personal sick time
  • Professional development stipend
  • Fertility Stipend
  • Wellness/fitness benefits
  • Fulltime
Read More
Arrow Right

Power Methodology Engineer, Data Center Hardware IPs

A senior power lead for power architecture solutions, specializing in areas like...
Location
Location
United States , Santa Clara
Salary
Salary:
191040.00 - 286560.00 USD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Extensive industry experience, with a specialization in low-power-processor architectures or power management
  • Expertise in ASIC/SoC power analysis and optimization techniques
  • Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
  • AI/ML Concepts: Familiarity with machine learning algorithms and their application to power simulation/optimization, as well as an understanding of NPU function and AI workload characteristics
  • Proficiency in hardware description languages like Verilog or VHDL, and scripting
  • Strong analytical skills and experience with power analysis tools (e.g., PowerArtist, PTPX)
  • Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and simulation/analysis tools
  • Strong analytical and problem-solving skills to tackle complex, multidisciplinary power and performance challenges
  • Several years of experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
  • Strong scripting and automation skills, preferably in Python
Job Responsibility
Job Responsibility
  • Focuses on optimizing the energy efficiency and power delivery of high-performance computing hardware used in large-scale AI and machine learning applications
  • Driving power methodology for AI-specific hardware components (like tensor cores and matrix multiplication engines) and using simulation tools (e.g., PowerArtist, PTPX) to estimate and optimize power consumption
  • Workload Optimization: Analyze the power and performance characteristics of AI, Graphics, Battery life WLs, especially specific WLs for NPUs, GPUs, and CPUs
  • Performance/Watt Optimization: Focus on maximizing performance while staying within strict power and thermal limits, which is critical for both data center and gaming applications
  • Power Optimization: Estimate and analyze power consumption at various stages of chip design (architecture, RTL, physical design)
  • Analysis and modeling: Creating power models and scripts for performance/power trade-offs
  • Methodology Development: Researching, developing, and deploying methodologies and automated flows (using scripting languages like Python or Perl) to enhance power analysis efficiency
  • Collaboration: Working with other teams, including RTL, Architecture, Physical Design, Emulation, software, Firmware to ensure power requirements are met across the hardware-software stack
  • Leadership: Mentoring junior team members and providing technical leadership on complex projects
  • Fulltime
Read More
Arrow Right

Senior SoC HW (Functional) Validation Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Hillsboro
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • Applied understanding of Computer Architecture and CPU/SoC validation principles, including: Understanding of SoC subsystem, SoC system level, and platform level functionality and writing scripts/software with industry standard languages like Python or C/C++
  • At least 5+ years of experience
  • Proficient communication, collaboration and teamwork skills and ability to lead, grow, and contribute to diverse and inclusive teams
  • Verification, logic development, validation, or validation tools experience as part of a CPU, SoC and/or IP development team
  • Leadership skills
  • Demonstrated validation expertise in one or more of the following: Functional: Core, cache Coherency/mesh/fabric, PCIe/ IO, Memory Controller, Power Management
  • Power and Performance
  • Automation, Content Creation, or Tools/Scripts Development
Job Responsibility
Job Responsibility
  • Own post-silicon validation of one of the following areas – functional validation of cache Coherency/mesh/fabric
  • Define, guide, and contribute to the implementation of silicon debug tools and capabilities
  • Become an expert on the overall architecture, implementation of complex features/flows/protocols, and their interactions with other parts of the SoC, with the platform, and with software
  • Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise
  • Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements
  • Apply your knowledge of validation principles and techniques and your judgement to write test plans and implement them by developing test content, scripts, tools and other validation collateral
  • Execute content in post-silicon, triage and debug failures
  • Apply your growth mindset to learn and adapt in a complex and dynamic environment
  • Engage with partners to drive continuous improvement to the design, to validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably
  • Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers
  • Fulltime
Read More
Arrow Right

Senior Performance Architect

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Hillsboro
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • 3+ years of experience developing SOC or IP performance models and benchmarks from conception to microarchitecture specification
  • Deep understanding of computer architecture, System on Chip (SOC) and system-software architectures, and their performance tradeoffs
  • Significant understanding of input/output (I/O), memory subsystems, coherency flows, interconnect, Quality of Service (QoS) traffic
  • Excellent communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
Job Responsibility
Job Responsibility
  • Develop performance modeling methodologies by creating and owning System on Chip (SOC) / Intellectual Property (IP) cycle-accurate/approximate performance models and analysis tools in C++ and Python
  • Use workload information and working with Micro-architects and Register Transfer Level (RTL) team to identify performance bottlenecks
  • Collaborate across functionally to propose architectural/microarchitectural changes and provide the required quantitative justification
  • Leverage AI tools and infrastructure for comprehensive performance modeling, including coding, performance tuning, analysis
  • Verify the correlation of the SOC performance models to the RTL implementation
  • Work closely with the product architecture System On Chip (SOC) architecture teams, IP architecture, to ensure our SOC and IPs enable performant, efficient, and industry-leading systems
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion
  • Fulltime
Read More
Arrow Right
New

Principal Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Mountain View
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • 9+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or systems
  • 5+ years’ industry experience of chip and/or computer architecture
  • 5+ years industry experience in Verilog or VHDL, C/C++, and scripting language such as Python, Ruby or Perl
  • CPU or Graphics core verification experience
  • In depth knowledge of verification principles, testbenches, stimulus generation, System Verilog, UVM, and coverage closure
Job Responsibility
Job Responsibility
  • Creation of complex verification environments and tests, pre-silicon functional verification at the block, chip and system level, reference modeling and post-silicon validation
  • Interact with architects and design engineers to create verification plans covering strategy, test environments & tests, and verification requirements for IP/SS/SOC level verification
  • Create and drive test-plans and test development to provide complete features coverage
  • Develop and implement technical solutions to complex quality and design challenges
  • Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage
  • Triage and debug testbench, simulation, and emulation fails
  • Develop Makefiles and scripts for scalable and efficient verification
  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment
  • Collaborate with teams across sites and geographies
  • Fulltime
Read More
Arrow Right
New

Senior Validation Engineer

The Artificial Intelligence Silicon Engineering team is seeking passionate, driv...
Location
Location
United States , Mountain View
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
  • OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Lead key components of tooling and infrastructure for validation of complex SOCs
  • Define, develop and deploy tools and methodologies for volume test execution and efficient silicon debug
  • Ensure robust infrastructure in place for Pre-Silicon SoC verification, Post-Silicon/FPGA validation
  • Work with Cross functional teams, Architecture, Design, Verification, Partner teams for project execution and also define validation tools/methodologies for next generation designs
  • Running tests, debugging failures, creating stress and performance scenarios to meet test plan goals
  • Actively participate in chip bring up and write test firmware to support various teams
  • Coach and mentor others in your areas of expertise
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion
  • Fulltime
Read More
Arrow Right
New

Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter
Job Responsibility
Job Responsibility
  • Responsible for Hierarchical Design Planning and partitioning strategies
  • Responsible for RTL to GDS implementation in Physical Design domain
  • Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential
  • Help influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach
  • Execute floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA)
  • Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification
  • Develop guidelines, checklists, and best practices for top-level physical design
  • Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes
  • Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset
  • Demonstrate technical expertise across various domains of Physical Design & Timing Signoff
  • Fulltime
Read More
Arrow Right
New

ASIC Verification - Team Lead

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Santa Clara
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Experience working with large verification projects, including cluster/subsystem and fullchip environments
  • Ability to lead large scale verification execution, driving multiple senior level verification engineers across geographic regions towards project completion
  • Develop comprehensive pre-silicon verification test plans based on design specifications and performance requirements
  • Create and maintain UVM/SystemVerilog-based testbenches for block-level, cluster-level, fullchip and emulation verification
  • Comfortable and experienced with AI based tools to accelerate productivity
Job Responsibility
Job Responsibility
  • Pre-Silicon Verification
  • Improves verification efficiency through new and updated methodologies or tools
  • Defines verification strategies and test plans
  • Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels
  • Drives the development of verification environments, runs, and debugs simulations to drive quality
  • Influences the product life cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
  • Leads application of random-stimulus, coverage, formal verification, or other verification techniques to find bugs and meet test plan goals
  • Performance
  • Works collaboratively with various teams to define performance modeling requirements and ensure technology development planning meets needs
  • Determines type of performance model needed and appropriate model fidelity
  • Fulltime
Read More
Arrow Right