This list contains only the countries for which job offers have been published in the selected language (e.g., in the French version, only job offers written in French are displayed, and in the English version, only those in English).
Join AMD’s SimNow AI team and lead the evolution of how we build, maintain, and scale large‑scale pre‑silicon simulation software using AI and large language models (LLMs). SimNow is an advanced C++ simulator that supports validation of the software‑visible behavior of next‑generation AMD designs. In this role, you will set technical direction and build production‑grade AI systems that automate device model generation, enable large‑scale refactoring, and transform how engineers interact with complex simulation infrastructure. You will work at the intersection of deep C++ systems engineering, AI/ML for code generation, and pre‑silicon validation workflows, collaborating closely with simulation engineers, hardware architects, and validation teams across AMD. You will operate as a technical leader, owning architecture decisions, mentoring other engineers, and driving adoption of AI‑assisted workflows across the organization.
Job Responsibility:
Architect end-to-end AI pipelines for SimNow automation, spanning specification ingestion, planning, multi-level C++ code generation, validation, and deployment
Lead design and code reviews, making technical decisions that balance scalability, safety, and long-term maintainability
Mentor engineers on modern C++ best practices, large-scale system design, and AI-assisted development techniques
Collaborate with SimNow core teams, hardware architects, and pre-silicon validation engineers to translate requirements into robust solutions
Design and build LLM-based agents that generate complex C++ device models, including state machines, register callbacks, serialization, and multi-layer architectures
Develop codebase-intelligence systems (e.g., RAG pipelines leveraging semantic analysis, clang tooling, cscope) to extract patterns from decades of C++ evolution
Implement closed-loop build–test–iterate workflows where agents generate code, compile it, run tests, analyze failures, and refine outputs safely
Extend Python-based test harnesses and build evaluation frameworks to measure correctness, specification compliance, and productivity impact
Design scalable prompt and context-engineering systems (templates, includes, pattern libraries) for complex multi-step agentic workflows
Build telemetry, metrics, and dashboards to understand AI effectiveness, quality, cost, and adoption
Instrument agent workflows with observability and feedback loops to support continuous improvement
Drive best practices for AI-assisted engineering across the pre-silicon validation organization
Requirements:
10+ years of professional C++ experience with large, complex codebases
Expert-level knowledge of modern C++ (C++11 and later), including templates, STL, RAII, smart pointers, move semantics, and advanced OOP patterns
Deep understanding of compilation pipelines, linking, symbol resolution, and debugging complex build failures
Proven experience designing and maintaining modular architectures in multi-million-line C++ systems
Experience modernizing or extending large legacy codebases without breaking existing functionality
Strong Python skills for test automation, evaluation, and infrastructure tooling
Production experience building AI-powered systems, developer tools, or code-generation pipelines OR a demonstrated strong trajectory with substantial hands-on LLM/agentic work
Experience designing multi-step agentic systems with tool use, state management, and iterative refinement
Strong prompt and context-engineering skills, including validation and guardrails
Experience defining metrics and evaluation strategies for code quality and correctness
BS, MS, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field
Nice to have:
Pre-silicon validation, functional simulation, or emulation workflows
Reading and interpreting hardware specifications (block diagrams, register maps, signal definitions)
Verilog/SystemVerilog familiarity or computer architecture background
Experience with clang/LLVM tooling or static analysis infrastructure
Track record of technical leadership in large engineering organizations