Fullchip Floorplan Design Engineer

• Own full-chip floorplanning (partitioning, macro placement, integration)
• Translate RTL → full-chip floorplan (chip structure, block definition)
• Plan pins, feedthroughs, and bus topology (incl. source-synchronous interfaces)
• Define repeater strategy for timing and signal integrity
• Optimize floorplan for timing, power, and area (PPA)
• Run feasibility / tradeoff analysis for floorplanning decisions
• Collaborate with RTL, architecture, DFT/DFX, and PD teams
• Use tools like Fusion Compiler / Innovus for implementation
• Build automation (Tcl / Perl / Python) to improve execution

• Experience in SoC physical design with successful tapeouts
• Strong ownership of full-chip floorplanning (partitioning, macro placement, integration)
• Solid understanding of physical design flows and impact on timing, power, and implementation
• Hands-on experience with Fusion Compiler or similar tools (e.g., Innovus)
• Experience with feedthrough planning, bus topology, and timing-aware floorplanning
• Understanding of SoC architecture (e.g., AXI, source-synchronous interfaces, test)
• Proven collaboration with RTL, IP, DFT/DFX teams
• Scripting skills (Tcl, Perl, Python, or Shell) for automation
• Experience with large-scale SoC designs and low-power considerations
• Experience improving design productivity through automation or advanced methods
• Bachelor's or master's degree in electrical engineering, computer engineering, or related field preferred

Benefits offered are described: AMD benefits at a glance