Fpga design verification engineer Job at Myticas Consulting (Ottawa)

Fpga Developer / Fpga Design Engineer (4g/5g Radio – Datapath / Ru Fpga Design)

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

Hands-on DSP (Digital Signal Processing) expertise including FFT, Beamforming, and Digital Filter implementation
Strong MATLAB / Simulink experience
SystemVerilog and RTL design experience for complex FPGA-based systems
Experience developing FPGA IP and architectures for 4G/5G Radio Units
Knowledge of AXI and Ethernet protocols
Experience with FPGA development tools including Altera Quartus and MATLAB/Simulink
Exposure to model-based design methodologies and FPGA implementation workflows
Understanding of wireless communications, 4G/5G radio architecture, O-RAN, LTE, eCPRI, CPRI, and PTP protocols is desirable but not mandatory
Experience optimizing FPGA resource utilization, timing closure, and high-performance datapath processing
Knowledge of high-speed interfaces such as Ethernet, PCIe, JESD204B/C, AXI, and SERDES technologies

FPGA Design Engineer

For this role, we are seeking an experienced FPGA design and verification engine...

Location

England , Stevenage

Salary:

80.00 - 90.00 GBP / Hour

Morson Talent

Expiration Date

Until further notice

Requirements

Ideally we are looking for candidates that are degree qualified (or equivalent) with significant experience in FPGA development
Competent VHDL Language and Design Skills
Competent Verification Skills using VHDL and SystemVerilog methodologies
A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs
Experience of professionally configuring and documenting designs
Experience of working as part of a large multidiscipline team

Job Responsibility

Generating complex FPGA architectures and design implementations (VHDL, Simulink etc), targeting Xilinx, Intel, Microsemi devices
Verifying complex FPGA implementations using VHDL and System Verilog\UVM test-bench methodologies
Using FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim)
Generating low-level software (C) to facilitate FPGA test and integration with the wider embedded system
Configuring and Documenting designs to a high professional standard
Working as part of a multidiscipline team to deliver complex FPGA based projects

Fulltime

FPGA Design Engineer

Location: Mountain View, CA (Remote). What will you do: Strong expertise on Arte...

Location

United States , San Jose

Salary:

95900.00 - 203500.00 USD / Year

Arrow Electronics

Expiration Date

Until further notice

Requirements

Strong expertise on Arteris/ NOC Design Toolset
At-least 5+ years of experience in Verilog Design
AMBA AXI bus along-with ARM or C based processor
Strong expertise along-with complex SoC/IP debug is must
At-least 5+ years of experience in System Verilog HVL and C/C++
AMBA AXI bus along-with ARM or C based processor
Bi-frost/Processor based C and SV/UVM mix Verification
Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure
Make/Perl/Python

Job Responsibility

Ensure customer satisfaction
Reporting to customers on daily or weekly progress effectively

What we offer

Medical, Dental, Vision Insurance
401k, With Matching Contributions
Short-Term/Long-Term Disability Insurance
Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
Paid Time Off (including sick, holiday, vacation, etc.)
Tuition Reimbursement
Growth Opportunities

Fulltime

Senior FPGA Design Engineer

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

Design and implement RTL using Verilog and SystemVerilog for complex FPGA systems
Translate high-level requirements into detailed architecture and design specifications
Execute full FPGA design flow including synthesis, place and route, and timing closure
Develop and optimize designs for high-speed, high-performance applications
Work across multiple clock domains including asynchronous CDC handling
Collaborate with verification teams to ensure functional correctness and coverage
Debug and resolve design, timing, and hardware issues at block and system levels
Support hardware bring-up, lab validation, and system integration activities
Utilize FPGA toolchains such as Xilinx Vivado or Intel Quartus
Implement and integrate high-speed interfaces such as PCIe, Ethernet, DDR, SPI, and I2C

Job Responsibility

Design and implement RTL using Verilog and SystemVerilog for complex FPGA systems
Translate high-level requirements into detailed architecture and design specifications
Execute full FPGA design flow including synthesis, place and route, and timing closure
Develop and optimize designs for high-speed, high-performance applications
Work across multiple clock domains including asynchronous CDC handling
Collaborate with verification teams to ensure functional correctness and coverage
Debug and resolve design, timing, and hardware issues at block and system levels
Support hardware bring-up, lab validation, and system integration activities
Utilize FPGA toolchains such as Xilinx Vivado or Intel Quartus
Implement and integrate high-speed interfaces such as PCIe, Ethernet, DDR, SPI, and I2C

Fulltime

Asic/Fpga Design Verification Engineer

We are the global test and automation specialists, powering next-generation tech...

Location

United States , North Reading

Salary:

98700.00 - 157900.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

3+ years of professional experience in digital logic verification or related roles
Experience with Cadence Xcelium or other industry-standard simulators
Strong experience with System Verilog and Universal Verification Methodology (UVM)
Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
Experience with RTL design using Verilog HDL
Familiarity with System Verilog assertion-based verification methodologies
Experience working within CI/CD development flows

Job Responsibility

Review design requirements and specifications
Write and review verification plans
Develop testbench architecture and implementation
Create reference models
Write System Verilog tests and develop UVM environments
perform debug
Collect, merge, and close functional and code coverage
Manage bugs and issues using a tracking tool
Collaborate closely with logic designers
Communicate technical status and risks to the team leader

What we offer

medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs
discretionary bonus(es) based on financial performance

Fulltime

Asic/fpga Design Verification Engineer

Our Logic Design Engineering (LDE) team is seeking a Digital Logic Verification ...

Location

United States , North Reading

Salary:

123100.00 - 196900.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

5+ years of professional experience in digital logic verification or related roles
Experience with Cadence Xcelium or other industry‑standard simulators
Strong experience with System Verilog and Universal Verification Methodology (UVM)
Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
Experience with RTL design using Verilog HDL
Familiarity with System Verilog assertion‑based verification methodologies
Experience working within CI/CD development flows

Job Responsibility

Review design requirements and specifications
Write and review verification plans
Develop testbench architecture and implementation
Create reference models
Write System Verilog tests and develop UVM environments
perform debug
Collect, merge, and close functional and code coverage
Manage bugs and issues using a tracking tool
Collaborate closely with logic designers
Communicate technical status and risks to the team leader

What we offer

medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs

Fulltime

Principal FPGA Design Engineer - 4G/5G Radio Systems

Are you a FPGA Design Engineer looking for a new opportunity? Are you looking fo...

Location

Canada , Kanata

Salary:

62.19 - 72.43 USD / Hour

Randstad

Expiration Date

June 29, 2026

Requirements

7+ Years of RTL Expertise: Proven track record in high-complexity FPGA design, specifically using SystemVerilog or Verilog. (Note: Candidate must be willing to work exclusively in a non-VHDL environment).
Altera/Intel Toolchain: Mastery of Quartus Prime for synthesis, place-and-route, and timing closure on high-density FPGAs.
DSP Modeling: Proficiency in MATLAB and Simulink for algorithmic modeling and fixed-point simulation prior to RTL implementation.
Protocol Mastery: Deep expertise in AXI (AXI4-Stream, AXI4-Lite) and Ethernet (10G/25G/100G) protocol implementation.
High Speed Interfaces: Practical experience with JESD204B/C, PCIe, and multi-gigabit SERDES transceivers.
Synchronization: Understanding of timing and synchronization protocols, such as PTP (IEEE 1588) and SyncE.
Wireless Infrastructure: Direct experience developing Radio Units (RU) or Massive MIMO systems.
Industry Standards: Functional knowledge of 3GPP physical layer specifications and O-RAN (Open RAN) Fronthaul interfaces (eCPRI/CPRI).
Signal Processing: Experience implementing Digital Up/Down Conversion (DUC/DDC), Crest Factor Reduction (CFR), or Digital Pre-Distortion (DPD) in hardware.
Advanced Verification: Experience with UVM (Universal Verification Methodology) and constrained-random testing to ensure 'first-time-right' silicon/FPGA bitstreams.

Job Responsibility

Define System Requirements: Translate high-level customer needs and 3GPP/O-RAN standards into detailed functional specifications for the entire FPGA ecosystem.
Drive 5G Roadmap: Architect FPGA IP specifically for 4G/5G Radio Units, ensuring designs align with industry trends and long-term organizational strategy.
Strategic Design Choices: Set the standard for product excellence by selecting optimal components and design methodologies to meet aggressive cost and performance targets.
High-Complexity RTL Development: Lead the implementation of complex logic blocks using SystemVerilog, focusing on high-speed Ethernet and AXI protocol integration.
Model-Based Design: Utilize MATLAB and Simulink to model signal processing algorithms before translating them into hardware-efficient RTL.
Ensure Design Integrity: Oversee the full validation lifecycle, from UVM-based simulation to hands-on system-level testing and timing closure using Altera Quartus.
Hardware-Software Synergy: Partner closely with software and RF teams to ensure seamless interoperability between hardware logic and low-level software drivers.
Technical Authority: Act as the primary consultant on critical, high-impact projects, providing 'whiteboard-level' solutions to unusually complex engineering hurdles.
Team Mentorship: Provide technical guidance to junior engineers, fostering a culture of best practices in RTL coding and version control (Git).
Executive Communication: Bridge the gap between engineering and management by communicating project progress, risks, and technical visions to senior leadership.

Fulltime

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Fpga Design Engineer

Silvus is seeking a full-time FPGA Design Engineer reporting to the Director of ...

Location

United States , Los Angeles

Salary:

95000.00 - 135000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant field
Minimum 2 years of demonstrated experience in FPGA design
Proven experience with multiple clock-domain, high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Experience with tcl or python

Job Responsibility

Digital design architecting for wireless communication projects
Fixed point design of signal processing blocks while working with systems engineers
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering Teams

Fulltime

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Fpga design verification engineer

Requirements

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