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As an FPGA Design Engineering Intern at Owl Cyber Defense, you will gain hands-on experience working with engineers who design and implement FPGA-based hardware for high-assurance cybersecurity products. You will support the development, simulation, and testing of VHDL/SystemVerilog designs that process and protect high-speed Ethernet data. This role offers an opportunity to learn about the design lifecycle for secure embedded systems, from hardware design and simulation through testing and validation, all within a collaborative engineering team that develops Owl’s advanced cross domain and data diode solutions.
Job Responsibility:
Assist in the design, simulation, and verification of FPGA modules using VHDL or SystemVerilog
Support development of packet-handling applications for high-speed Ethernet systems
Contribute to testbench development and simulation using tools such as ModelSim or Cadence Xcelium
Collaborate with senior FPGA engineers to analyze and debug system-level designs
Help implement communication protocols from design specifications and requirements
Participate in hardware bring-up and testing on custom FPGA platforms
Learn to use FPGA toolchains such as Vivado or Quartus for synthesis and implementation
Document findings, procedures, and test results to support engineering deliverables
Requirements:
Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related discipline with a focus on FPGAs or Embedded Logic
Coursework or project experience in FPGA design, digital systems, or embedded hardware development
Familiarity with VHDL or SystemVerilog
Exposure to HDL simulation tools (ModelSim, Cadence Xcelium, etc.)
Understanding of digital design fundamentals, state machines, and timing analysis
U.S. Citizenship required
candidates must be able to obtain and maintain a U.S. Government security clearance
Nice to have:
Basic knowledge of networking concepts (Ethernet, TCP/IP, UDP) is a plus
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