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Foundry Interface Engineer

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Location:
Singapore , Singapore

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Category:
IT - Software Development

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Job Description:

The Foundry Interface Engineer will engage with Foundry partners/third-party vendors as well as internal teams to continuously improve the design of our ASICs. This work will include partnering with OSAT to continuously monitor and review production wafer test data, and work with standard cell level circuit designers to analyze the results. Based on the analysis the engineer will make requests to the foundry for process fine tuning.

Job Responsibility:

  • Engage with Foundry partners/third-party vendors to manage foundry PDK/DK and design library collaterals
  • Guide internal IP/design teams on appropriate usage of technology attributes/offerings in accordance with product requirements
  • Collaborate with internal third-party infrastructure, customization, test-chip, methodology, and packaging and product test engineering teams for seamless execution of product bring-up and productization
  • Review and assess Foundry silicon data against SPICE/design goals and compile SPICE to Silicon gap analysis
  • Drive foundry partners on CIPs to improve foundry process to meet technology entitlement and product goals
  • Work with foundry to identify potential device parameter changes to enable efficient low-voltage operation
  • Work closely with circuit designers to determine what device improvements could improve circuit performance and energy efficiency
  • Work with test engineers to analyze and validate production wafer data
  • Contribute to binning strategy to maximize parametric yield

Requirements:

  • 5 + years of post-education experience in FAB/Fabless environments, technology definition and bring-up, device/process architecture, and NPI
  • Experience with foundry design kit, SPICE, DR/DRC evaluation, SPICE to Si assessment
  • Experience with advanced node device physics (e.g. FinFET/GAA), backside power, product design phases
  • Experience with product KPIs, DTCO, and parametric, DLY/PLY analysis/gap closure
  • Understanding of low power design techniques (e.g., Vmin reduction, power gating, multi-voltage design, chip power, clock network and optimization)
  • Understanding of layout effects and impact to circuit design

Nice to have:

  • Master's degree or PhD in Electrical Engineering, Physics, or other related Engineering field with emphasis on semiconductor materials/devices and device physics
  • Production test development experience
  • Familiar with advanced FinFET technology nodes (3nm and 2nm)
  • Familiar with PDK and device models
  • Previous work experience at semiconductor foundries
  • Familiar with standard cell design and layout
What we offer:
  • Remote work
  • Medical insurance
  • Flexible time off
  • Retirement savings plans
  • Modern family planning

Additional Information:

Job Posted:
May 03, 2026

Employment Type:
Fulltime
Work Type:
Remote work
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