Formal Verification Engineer

• Collaborating with architects and designers to understand the design intents
• Creating and executing formal verification plans for design blocks
• Writing and debugging properties to verify the design, analyzing signatures and pushing for the resolution
• Optimizing runtime using formal techniques
• Collecting and reporting status and progress
• Improving formal setups based on feedbacks from reviews, metrics, etc
• Leading and coordinating verification activities for a small team
• Training and coaching junior engineers
• Developing working procedures, flows and infra
• Handling complicated formal problems

• Combined ASIC/FPGA design and verification experience
• Verify complex IPs including I/O virtualization, PCIe Root Complex/End Point, and high-speed inter-chiplet interconnects using advanced formal verification methodologies
• Develop and execute formal functional and security verification strategies to ensure industry-leading design quality and coverage
• Apply expertise in high-speed I/O protocols, IP verification, and formal verification technologies to validate next-generation semiconductor designs
• Drive adoption of cutting-edge formal verification and automation techniques to improve verification efficiency and accelerate closure
• Provide technical leadership, mentorship, and methodology guidance across formal verification projects and teams
• Demonstrate strong hands-on experience with AI-based formal verification, including AI-assisted property generation, proof optimization, coverage analysis, root-cause debugging, and verification closure
• Collaborate closely with architecture, RTL design, DV, and silicon teams from concept through tapeout and post-silicon validation
• Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC), and/or academic formal methods
• Expertise in a formal property language (SVA preferred), abstraction techniques, formal sign-off and commercial formal tools (VC-Formal, JasperGold, Questa Formal, etc.)
• Extensive experience verifying complex, packet or control based designs
• Familiarity with industry standard high-speed protocols such as PCIe, SATA, USB, AXI, etc
• Experience with verification of Hardware-Firmware interaction is highly desirable
• BS (or higher) degree in Electronics/Electrical or Computer Engineering desired

Experience with verification of Hardware-Firmware interaction is highly desirable

Benefits offered are described: AMD benefits at a glance