Firmware Engineer – GPU & SOC Architecture Job at AMD (Markham)

SoC Systems Software Engineer

AWS designs custom SoCs (System on Chips) that power the world's largest machine...

Location

United States , Cupertino; Austin

Salary:

168100.00 - 261500.00 USD / Year

Amazon

Expiration Date

Until further notice

Requirements

6+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
Experience as a mentor, tech lead or leading an engineering team
7+ years of professional experience developing firmware, drivers, runtime software, or low-level systems software for custom hardware (SoCs, ASICs, GPUs, CPUs, FPGAs)
Experience programming in C++, Python, and/or Rust (preference for at least 2)
Knowledge of SoC, CPU, GPU, and/or ASIC architecture and micro-architecture

Job Responsibility

Develop and own components of our SoC models, both single-chip and at the datacenter-scale level
Debug complex hardware/software interactions across the full software stack — from register-level bring-up on functional models and emulators, to performance analysis on live silicon
Collaborate with chip architects, RTL designers, modelers, compiler engineers, and ML framework teams to co-design and validate the hardware/software interface
Contribute to the design of hardware features by providing a software perspective early in the chip development cycle
Build tooling, test infrastructure, and automation that accelerates development for yourself and your teammates

What we offer

health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
401(k) matching
paid time off
parental leave
sign-on payments
restricted stock units (RSUs)

Fulltime

New

GPU Hardware Security Architect

We are seeking a self-motivated GPU Hardware Security Architect to join our grow...

Location

United States , Santa Clara

Salary:

232000.00 - 348000.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Relevant work experience focused on computer architecture and security
strong understanding of factors influencing register and firmware access protections at chip, system, and product levels
thorough knowledge of RTL design and/or verification
proven track record of providing and following through with pragmatic security requirements
expert at tackling multi-variable problems via system-level modeling, testing and characterization, trend analysis/projection, and model verification
Computing and Graphics architecture
a drive to continuously learn and expand architectural breadth and depth
understands GPU security/power/performance, SW and FW access, and system-level trade-offs
Graphics Shader behavior is a benefit
knowledge of Machine Learning and AI usage is a benefit

Job Responsibility

Investigate and architect next‑generation GPU IP features that enhance protection of register access and sensitive customer data
research and quantify attack vectors through which bad actors can gain access to customer data or GPU configuration
experienced in the use of AI tools to identify and resolve security issues
ensure AMD's security offerings meet industry standards and anticipate industry trends
work with AMD SoC and other IP teams to track trends and development directions for GPU security
write and deliver architectural specifications to development teams (HW, SW, Firmware, etc)
architect new GPU algorithms to improve GPU security without compromising performance
provide technical and cross-functional debug support to execution teams
perform design and threat analysis of firmware and hardware
deliver architecture specifications and/or review proposals from internal/external sources

Fulltime

New

FPGA Development Engineer

The AMD Data Center GPU Remote Management team is seeking a talented FPGA Develo...

Location

United States , Austin

Salary:

163200.00 - 244800.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Bachelor’s / Master’s degree (preferred) in Electrical Engineering, Computer Science, Computer Engineering
Strong communicator and team player in fast-paced environments
Self-starter who can work independently and complete tasks
Experience with FPGA, firmware, and embedded system testing
Xilinx design (Block Design, AXI IP) and custom IP integration
Programming in Verilog/SystemVerilog, Python, TCL, Bash, C/C++ (Linux)
Ability to read schematics and apply verification methodologies (Mentor)
Knowledge of embedded protocols (I2C, SPI, USB, PCIe, TCP/IP)
Familiar with BMC management and protocols (IPMI, MCTP, PLDM, Redfish)
Experience with ARM-based systems, build tools (make, git), and CI/CD (Jenkins)

Job Responsibility

Develop complex FPGA-based digital designs using SoCs with embedded processing, high-speed interfaces, and custom IP
Define FPGA architecture, requirements, and supporting documentation
Translate system-level requirements into FPGA design specifications
Write high-quality Verilog/SystemVerilog to meet performance, quality, and schedule targets
Develop and execute test and verification strategies for FPGA designs
Drive best practices for design quality, development processes, and continuous improvement
Create modular, reusable FPGA IP for current and future projects
Support debug and defect resolution, including validation, logging, and root-cause analysis

Fulltime

Principal Product Development Eng. - System Level Test

We are the New Product Introduction (NPI) test engineering team defining and pro...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Knowledge or working experience on GPU architecture, X86 architecture, SoC design and power management features
Experience with SOC (System-On-Chip), Firmware and Software interaction
Software programming and scripting proficiency (Java, Shell script, Perl, Ruby, Python)
Proficiency in Windows, and Linux operating systems
10 years or more industry experience

Job Responsibility

Accountable to drive and develop SLT solutions to meet business milestone, cost and quality in system level area
Solves complex, novel, and non-recurring problems
initiates significant changes to existing processes/methods and leads development and implementation
Conduct engineering evaluations and analysis to drive closure of production issues
Develop and architect SLT logging or data collection flow in manufacturing
Influences technical decisions that have a significant impact on final product
Involves collaboration on or assuming the consultative or leadership responsibilities for a specific project or for product development initiatives
May provide technical supervision or mentoring junior engineers
Upscale overall team capabilities on low level system debug for AMD data center product families

Fulltime

Power and Performance Engineer

AMD's Computing and Graphics business unit is seeking a technical leader to driv...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

PhD or MS in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a related technical field
Prefer 8+ years of industry experience
Experience profiling software workloads on CPUs and GPUs
Knowledge of defining low-level software interfaces to influence hardware performance and power behavior
Background in SOC hardware design, clock distribution, power delivery and performance
Experience profiling and tuning hardware/software stacks to achieve power and performance efficiency on benchmark workloads
Prior algorithm development in C or Python
MATLAB experience preferred
Expertise in algorithm development for predictive systems using regression and classification frameworks for complex datasets
Experience with system and SoC control firmware, including RTOS and bare-metal development

Job Responsibility

Develop and architect new power algorithms and software features using state-of-the-art techniques, including classifiers, regression models, machine learning approaches for CPU/GPU power and performance optimization
Define and implement software interfaces that influence and optimize hardware behavior across the SoC
Prototype and develop new firmware for complex power-control algorithms throughout the SoC roadmap
Profile emerging NN and LLM (Agentic) workloads on client platforms
tune algorithms to optimize power during active, high-load, and interactive usage scenarios
Analyze power and performance benchmarks to identify opportunities for efficiency improvements
Architect, implement, and optimize control software and firmware features to achieve product-level power targets
Drive cross-organization alignment for innovative power-reduction methodologies and ensure convergence across design teams
Collaborate with global architecture and design teams to implement and validate SoC power-management solutions
Optimize real PC use cases for both absolute power and performance-per-watt

Fulltime

Slt Product Development Engineering Manager

We are a results-driven Central Engineering team delivering System Level Test (S...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor's degree in Electrical and Electronic Engineering/Computer Engineering
Master's degree in Electrical and Electronic Engineering/Computer Engineering
Experience with CPU, GPU, system architectures
Strong people, communication & stakeholder management skills
Test & characterization, Programming & automation/AI assisted skills & experience preferred
Hand on experience in a team management role
Technical and specialized knowledge in Test, Characterization, Platform Engineering areas such as OS kernel, Driver, BIOS firmware development, Diagnostics or System Debug with semiconductor industry experience in product development for computing/graphics SOCs
Demonstrated object-oriented programming experience in scripting and/or programming languages such as python and java

Job Responsibility

Lead efforts in developing System Level Test (SLT) solutions within the stipulated cost, quality, yield and organizational strategic constraints
Collaborate with Design, Validation, Platform Engineering, Diagnostic and Tools teams to determine SLT coverage, content, characterization requirements and root cause resolution for SLT device failures
Lead efforts in the New Product Introduction phase to validate new product features, test conditions, Test methodologies and Test content
Drive quality & margin improvement in the Sustaining phase
Lead bounding box performance characterization efforts and innovation
Product health and cost target attainment
Drive yield and quality improvement activities through data analysis, debug, root-cause and implementation into production
Drive unit-cost reductions through Test-Time reduction and content optimization methodologies
Lead efforts in defining and developing SLT Equipment, software Infrastructure and test content within required Product timelines and quality goals
Manage resources for agility, focus and execution efficiency to deliver outcomes/results aligned to organization goals

Fulltime

Principal Engineer, ASIC Development Engineering (Frontend Architect - AI Storage Solutions)

In this Frontend Architect position, you will develop AI Storage Solutions based...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelors or Masters or PhD in Computer/Electrical Engineering with 8+ years of hands-on Architecture experience authoring specifications
Strong technical background architecting SoC and I/O subsystems involving PCIe and PCIe-DMA engines, or UCIe or CXL or UAL
Strong IO subsystem microarchitecture, technical, and working knowledge of the PCIe/UCIe protocol specifications
Knowledge of I/O Subsystem and DMA interactions with internal embedded processor-subsystems (x86, RISC-V or ARM) and external host CPU
Good understanding of computer/graphics architecture, ML, LLM
Architecting an GPU/TPU/xPU Accelerator systems with optimized high bandwidth memory hierarchy and frontend architecture for multi-trillion parameter LLM training/inference including Dense, Mixture of Experts (MoE) with multiple modalities (text, vision, speech)
Deep experience optimizing large-scale ML systems, GPU architectures
Proficiency in principles and methods of microarchitecture, software, and hardware relevant to performance engineering
Multi-disciplinary experience, including familiarity with Firmware and ASIC design
Expertise in CUDA programming, GPU memory hierarchies, and hardware-specific optimizations

Job Responsibility

Responsible for driving the SoC architecture, with a particular focus on I/O subsystems connected over UCIe, PCIe, UAL or CXL
Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric
Create flexible and modular I/O subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors
Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets
Define I/O subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and SoC CPUs on the device side and Host CPUs
Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase
Responsible for improving the AI/ML ASIC Architecture performance through hardware & software co-optimization, post-silicon performance analysis, and influencing the strategic product roadmap
LLM Workload analysis and characterization of ASIC and competitive datacenter and AI solutions to identify opportunities for performance improvement in our products
Experience architecting one or some components of AI/ML accelerator ASICs such as HBM, PCIe/UCIe/CXL, NoC, DMA, Firmware Interactions, NAND, xPU, fabrics, etc
Drive the AI Storage Solutions frontend system architecture with GPU/TPU/NPU/xPU to match or exceed the nextgen HBM bandwidth

Fulltime

Lead Platform Emulation Engineer

The focus of this role is to plan, build, execute the verification, validation/e...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience
Experience with BIOS/OS bring up on full X86 SOC emulation platform
Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem
Proficient in debugging firmware and RTL code using simulation tools
Good understanding of PCIe/USB/Ethernet standards
safety concepts/IPs
Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC
SOC design model build experience
Experienced with Verilog, System Verilog, C, and C++
Experience in writing and debugging testbenches

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed Pre-Silicon Emulation tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test or infra issues
Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment
Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation
Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug

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Firmware Engineer – GPU & SOC Architecture

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