Fellow - FPGA architecture

• Own FPGA configuration architecture, including bitstream, boot flows, interfaces, compression, security, and reliability
• Define next‑generation Partial Reconfiguration architecture for low‑latency, secure dynamic updates
• Drive innovation in runtime reconfiguration for high‑availability and adaptive systems
• Architect readback, debug, and observability infrastructure for validation and in‑field diagnostics
• Define configuration security, including secure boot, key management, and update flows
• Drive system trade-offs across configuration bandwidth, latency, and power, including memory and interconnect interactions
• Develop clear architecture specifications for configuration, PR, and debug subsystems
• Align with software/tools teams for end‑to‑end configuration and PR flows
• Collaborate with silicon and design teams for scalable high‑quality implementation
• Influence product roadmap and customer engagement for PR‑driven solutions
• Mentor architects and elevate FPGA architecture standards across the organization

• Strong Expertise in FPGA configuration, Partial Reconfiguration, and bitstream architecture
• Experience with readback/debug infrastructure and field diagnostics
• Background in ASIC/SoC design flows
• Familiarity with FPGA toolchains (synthesis, P&R, PR flows)
• Ability to define architecture across silicon, tools, and software layers
• BS, MS, or PhD in Electrical/Computer Engineering or related field
• Recognized technical leader in FPGA systems or architecture with significant architectural contributions, patents, publications, or industry impact

Benefits offered are described: AMD benefits at a glance.