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DV Intern

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Etched

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Location:
United States , San Jose

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

Not provided
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Job Description:

As a Design Verification intern, you will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Job Responsibility:

  • Ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready
  • Collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack

Requirements:

  • Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field
  • Familiarity with high-speed digital logic
  • Exposure to ASIC or SoC design concepts
  • Familiarity with SystemVerilog, UVM, or Python
  • Familiarity with verification work and writing test benches
  • Familiarity with physical design flows and tooling
  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Nice to have:

  • Familiarity with transformer models and machine learning
  • UVM or formal verification experience
  • Ability to program with Python or another scripting language
What we offer:
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
  • Direct mentorship from industry leaders and world-class engineers
  • Opportunity to work on one of the most important problems of our time

Additional Information:

Job Posted:
February 18, 2026

Employment Type:
Fulltime
Work Type:
On-site work
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