Digital Verification Engineer Job at Sandia National Laboratories (Albuquerque)

Job Description

Sandia National Laboratories is seeking a Digital Verification Engineer (R&D Electrical Engineer) with expertise in formal verification tools to ensure the correct functionality of ASIC and FPGA designs. The ideal candidate will have hands-on experience with VHDL and Verilog design languages and be proficient in using SystemVerilog Assertions (SVA) within formal verification environments. Success in this role requires a strong foundation in digital design principles, a detail-oriented and logical approach to problem-solving, and excellent written communication skills.

Job Responsibility

Translate digital design requirements at various development stages into precise, unambiguous checks against the implementation
Adapt diverse requirements including functionality, safety, and information protection into SystemVerilog Assertions (SVA) for verification
Evaluate trade-offs in formal analysis complexity to ensure verification tasks remain tractable and efficient
Collaborate closely with designers, system engineers, and other verification specialists to deploy systems that are verifiably correct
Produce clear, concise, and well-documented archival reports detailing verification activities and results
Present verification findings at technical reviews to peers and customers
Continuously learn and apply new formal verification techniques and methodologies

Requirements

A Bachelor's degree in a relevant discipline, or an equivalent combination of directly relevant education and engineering or scientific experience that demonstrates the knowledge, skills, and ability to perform independent research and development
Ability to obtain and maintain a DOE Q-level security clearance

Nice to have

Graduate degree in Electrical Engineering or a highly related field where an independent research project was a graduation requirement (e.g., independent project, thesis, or dissertation)
Ability to work independently and collaborate well in a multidisciplinary team of designers and test engineers
Outstanding verbal and written skills, including the ability to develop and present briefings that are clear and compelling
Several years of experience applying formal verification techniques to FPGA or ASIC designs
Proficiency with VHDL, Verilog, and SystemVerilog Assertions (SVA)
Strong analytical skills with meticulous attention to detail in both technical work and documentation

What we offer

Challenging work with amazing impact that contributes to security, peace, and freedom worldwide
Extraordinary co-workers
Some of the best tools, equipment, and research facilities in the world
Career advancement and enrichment opportunities
Flexible work arrangements for many positions include 9/80 (work 80 hours every two weeks, with every other Friday off) and 4/10 (work 4 ten-hour days each week) compressed workweeks, part-time work, and telecommuting (a mix of onsite work and working from home)
Generous vacation, strong medical and other benefits, competitive 401k, learning opportunities, relocation assistance and amenities aimed at creating a solid work/life balance

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Digital Verification Engineer

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