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SCALINX’s Digital Verification team is seeking a dynamic and highly motivated Digital Verification Engineer who will actively participate to ASIC digital verifications, at both IP level and ASIC Top level. In this role, the candidate will be particularly involved in the verification of the digital processing functions of the SCALINX ASICs, in close collaboration with engineers from other teams (Digital Design, Software and Silicon Validation)
Job Responsibility:
Write Subsystems and Top-Level verification plans, to meet ASIC Functional Requirements
Implement Verification Methodologies and participate to Flow improvements
Develop Subsystems and Top Level testbenches and self-checking testcases
Implement RTL and GLS (Gate Level Simulations) regressions, including coverage metrics
Support the Software team activities, including on the Emulation platform
Support the Silicon Validation team for the evaluation of the manufactured SoC
Work in team to successfully verify state-of-the-art SoCs
Requirements:
MSc or PhD in Electrical Engineering or equivalent
at least 3 years of hands-on experience in Digital Verification
a solid background in digital electronics and signal processing
a solid knowledge in System Verilog language for Verification
a solid knowledge in Python, including Object Oriented Programming
a solid knowledge in scripting languages such as Tcl, Makefile, etc.
Team player with a critical attitude and sense of initiative
Good analytical and problem-solving skills
Fluent in English (oral and written)
Nice to have:
UVM methodology
AMBA busses verification (APB, AXI, AHB)
CPU verification (ARM, RISC V) and C-oriented testing
Verification of Interfaces such as Ethernet, ADC/DAC
Verification of digital functions for as ADC, DAC and/or RF transceivers