CrawlJobs Logo

Digital Signal Processing Ic Designer

minalogic.com Logo

Minalogic

Location Icon

Location:
Italy , Milan

Category Icon

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

Not provided

Job Description:

iNGage is hiring a Digital Signal Processing IC Designer to complement and strengthen its ASIC design team for MEMS inertial sensors. Based in Milan as part of iNGage's ASIC design team, you will be responsible for developing and validating digital design blocks, as well as sensor compensation and calibration loops. Based in Grenoble (FR) and Milan (IT), iNGage is a start-up company which is bringing to market disruptive high-performance MEMS inertial sensors (accelerometers, gyros, IMUs) and pressure sensors for GPS-free navigation in autonomous mobilities. With a patented breakthrough technology developed at CEA-Leti in partnership with PoliMi, we push the limits of high-performance MEMS navigation sensors to make them accessible to high-volume applications such as industrial robotics and automotive

Job Responsibility:

  • Developing and validating digital signal processing chains, digital calibration and compensation loops for next-gen IMUs
  • Contributing to the ASIC digital implementation flow, including RTL design, synthesis and physical integration
  • Collaborating with cross-functional teams (internal and external design house) working on analog mixed-signal design, system architecture and silicon validation

Requirements:

  • Design, modeling and implementation of DSP chains for IC systems (using Simulink, Matlab, Phython, SystemVerilog)
  • Deep understanding of DSP building blocks (discrete-time filters, multirate processing and sample rate conversion architectures)
  • Familiarity with Cadence tools (or equivalent) for digital ASIC design and implementation
  • Knowledge of MEMS IMUs architectures is a strong plus

Nice to have:

Knowledge of MEMS IMUs architectures is a strong plus

What we offer:
  • Be part of an ambitious sensor startup with cutting-edge technology
  • Work on major tech challenges with high industrial impact
  • Thrive in a high level international dynamic R&D environment
  • Flexible Work environment

Additional Information:

Job Posted:
May 04, 2026

Employment Type:
Fulltime
Work Type:
On-site work
Job Link Share:

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Digital Signal Processing Ic Designer

Analog/Mixed-Signal IC Design Director

SCALINX is seeking a highly influential Analog/Mixed-Signal IC design team leade...
Location
Location
France , Paris/Caen/Grenoble
Salary
Salary:
Not provided
scalinx.com Logo
SCALINX
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proven industrial experience in: Architecture/design & validation of high-speed Nyquist-Rate data converters IP blocks (time-interleaved pipeline/SAR ADC architecture & current-steering DAC architectures)
  • Architecture/design of calibration circuits enhancing data converters performance
  • Integration of high-speed data converters IP blocks in complex mostly digital SoC (with strong knowledge of mixed-signals verification strategies/tools, signal integrity/power integrity & crosstalk issues)
  • Strong understanding of clocking circuit concepts and design trade-off to implement high-performance, high-speed data converters
  • Expert in AMS design/layout methodology
  • Experience in supervising mixed-signals designers and able to dive into technical details (down to transistor level)
  • Work across teams: Strong ability to resolve complex cross-functional issues
  • Design experience in advanced CMOS process
  • Excellent verbal and written communication (English required)
  • 15+ years of experience in IC design and technical leadership
Job Responsibility
Job Responsibility
  • Manage a team of ~25 people including architects and AMS design/layout engineers in the field of deep sub-micron technology SoCs
  • Lead all aspects of design from concept to production, including architecture, specifications, transistor-level design, modelling, verification, layout, post-silicon validation support, productization support, etc.
  • Lead cross-functionally to ensure program cohesion with teams such as marketing, systems design, digital front-end/back-end teams, validation, productization, quality, applications, packaging, etc.
  • Ensure quality and reliability standards are met for volume production
  • Develop methodology and processes for “first time right” products
  • Participate in communication with high-profile customers
  • Actively participate in the technology roadmap definition
  • Report development progress to executive management
  • Fulltime
Read More
Arrow Right

Senior Digital IC Design Engineer

SCALINX’s design team is seeking a dynamic and experienced digital designer who ...
Location
Location
France , Paris; Caen; Grenoble
Salary
Salary:
Not provided
scalinx.com Logo
SCALINX
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • MSc or PhD in Electrical Engineering or equivalent
  • Very good understanding of the entire digital IC design flow from RTL to GDSII
  • Strong expertise in digital electronics and signal processing
  • Proven experience in digital IC projects and technical leadership roles
  • Strong experience with ARM or RISC-V based SoC platform design
  • Solid experience with high-speed serial interfaces (JESD204, Ethernet, PCIe…)
  • Expertise in digital hardware description languages (VHDL or Verilog) and SystemVerilog
  • Experience with Cadence, Synopsys or Siemens RTL design flow
  • Proven experience with GIT and Linux systems
  • Skilled in scripting languages (Python, TCL, Perl)
Job Responsibility
Job Responsibility
  • Design of complex RTL blocks based on micro-architecture specifications
  • Top level integration of various RTL blocks and complex IPs
  • Execute complete LINT/CDC/RDC checks
  • Write SDC constraints to run logical synthesis
  • Write detailed design documentation in accordance with company QA policy
  • Generates KPI and report progress to the Program Manager
  • Timely deliver state-of-the-art RTL package to Digital Verification, DFT and Back-End teams
  • Lead and support digital design work-packages from RTL to netlist
  • Animate design reviews
  • Participate with the other project technical leaders in the definition of the IC architecture specifications and verification methodology
Read More
Arrow Right

Silicon Design Engineer

The AMD SerDes Technology Group develops high-performance, multi-protocol wireli...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Layout design experience in lower process nodes (7nm or below)
  • Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
  • Good understanding of high speed critical signal routing and shielding
  • Strong in physical design verifications (LVS/DRC/ERC/ANT/ESD/etc)
  • Familiarity with circuit design concepts/flows and IC manufacturing processes
  • Experience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET process is a plus
  • Experience with digital on top integration flow or digital SOC flow is a benefit
  • Experience with Cadence SKILL and other programming is a benefit (Perl, Pythong, Tcl, etc ...)
  • Ability to work closely with the remote & different time zones design teams
  • Excellent team player and good communication skills
Job Responsibility
Job Responsibility
  • Layout design of high speed and high performance SerDes analog mixed signal circuit in accordance to project requirements and specifications
  • Block level physical implementation which includes floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout
  • Participate in post-layout circuit performance analysis
  • Participate in block/IP/chip level integration activities
  • Estimate realistic schedule, track and report clear progress and status
  • Strong participation in defining layout methodology and flow
  • Driving layout productivity improvement initiatives (i.e: pcell development and automation)
  • Other responsibilities which include supervision of layout resources (onsite and offsite), assessing and correcting layout quality issues, and providing feedback to design teams
  • Fulltime
Read More
Arrow Right

Staff Engineer, ASIC Development Engineering

We are seeking a highly skilled High-speed SERDES IO PHY Layout designer with 5 ...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field
  • 5-10 years of experience in IO/Analog mixed-signal IC layout design and block level PnR
  • Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics
  • Hands-on experience with custom layout design for various analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs, and ESD circuits
  • Familiarity with custom digital layout (i.e. high speed logic paths)
  • Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding)
  • Strong understanding of analog/IO design principles, including parasitic effects
  • Aware of layout techniques to mitigate ESD, latch-up issues
  • Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 7nm and below
  • Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating
Job Responsibility
Job Responsibility
  • Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability
  • Collaborate with design engineers to understand design requirements and translate them into precise layouts
  • Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently
  • Work experience of block PnR to closely interact with physical design team ensuring area/timing/backend compatibility of custom blocks into the overall chip design
  • Identify and resolve layout-related issues, providing creative solutions to meet design specifications
  • Conduct layout reviews and provide technical feedback to improve layout practices and methodologies
  • Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes
  • Fulltime
Read More
Arrow Right

Senior Analog Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...
Location
Location
India , Hyderabad
Salary
Salary:
Not provided
synopsys.com Logo
Synopsis Engineering
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • MTech/MS with 2+ years or BTech/BS with 4+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field)
  • Proven expertise with FinFET technologies and CMOS tape-outs
  • Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures
  • Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC)
  • Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance
  • Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating)
  • Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators
  • Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results
  • Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk)
  • Excellent communication and documentation skills
Job Responsibility
Job Responsibility
  • Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications
  • Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed
  • Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality
  • Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance
  • Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews
  • Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements
  • Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates
What we offer
What we offer
  • Comprehensive medical and healthcare plans that work for you and your family
  • In addition to company holidays, we have ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Save for your future with our retirement plans that vary by region and country
  • Competitive salaries
  • Fulltime
Read More
Arrow Right

Staff Analog Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...
Location
Location
India , Hyderabad
Salary
Salary:
Not provided
synopsys.com Logo
Synopsis Engineering
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field)
  • Proven expertise with FinFET technologies and CMOS tape-outs
  • Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures
  • Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC)
  • Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance
  • Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating)
  • Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators
  • Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results
  • Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk)
  • Excellent communication and documentation skills
Job Responsibility
Job Responsibility
  • Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications
  • Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed
  • Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality
  • Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance
  • Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews
  • Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements
  • Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates
What we offer
What we offer
  • Comprehensive medical and healthcare plans that work for you and your family
  • Time Away: In addition to company holidays, we have ETO and FTO Programs
  • Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Retirement Plans: Save for your future with our retirement plans that vary by region and country
  • Competitive salaries
  • Fulltime
Read More
Arrow Right

Principal Signal Integrity Engineer

We are seeking a seasoned Signal and Power Integrity Engineer with expertise or ...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • MS or PhD in Electrical Engineering
  • Excellent analytical and problem-solving skills along with attention to details
  • Need a self-starter, someone able to drive tasks independently and efficiently to completion
  • Strong/effective communication skills
  • Enthusiastic team-first mentality
  • Experience with PCB, Package and IC level power delivery networks
  • Experience in silicon packaging and PCB design for signal and power integrity
  • Experience with high-speed digital signaling interfaces such as PCIE, GDDR6, HDMI
  • Expertise in electrical modeling EDA and AMS tools such as ADS, HFSS, SIwave, HSPICE
  • Expertise in electromagnetic theory and circuit analysis
Job Responsibility
Job Responsibility
  • Responsible for Signal Integrity and Power Integrity simulations at feasibility, pre-layout, post-layout phases of AECG characterization board and demo board design. Establish design and layout guidelines
  • Responsible for coordinating with HW design team, layout team, NPI and manufacturing vendors to resolve SI/PI related issues
  • Responsible for end-to-end channel simulations for multi gigabit serial lines like 56Gbps, 112Gbps and beyond
  • Responsible for PI analysis simulations of HBM/ /DDR4/LPDDR4/DDR5/LPDDR5 and other memory buses
  • Responsible for characterizing the various interfaces in the product and verifying the simulations against measurements
  • Responsible for preparation of and implementing checklists for various stages of PCB development
  • Worked with architecture team, package design team and PCB design team for future PCB technology
  • Update the SIPI design and analysis flow and automate the process
Read More
Arrow Right

Analog IC Design Architect

Our Hardware Engineers at Synopsys are responsible for designing and developing ...
Location
Location
United States , Boxborough
Salary
Salary:
136000.00 - 204000.00 USD / Year
synopsys.com Logo
Synopsis Engineering
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • >15 years experience in PHY analog design, including pre-silicon and post-silicon validation
  • Strong knowledge of physical IP such as SERDES, DDR/HBM or Die to Die IO Interface
  • Expertise in design trade-offs, flows, and methodologies
  • Skilled in generating and supporting documentation through written specifications, and communicating those specifications within a design team and to external customers
  • Able to work across a multi-site team to communicate ideas, understand problems, and find solutions to create a leading-edge design
  • Skilled in troubleshooting and debug of mixed-signal interfaces
  • Proficiency in using industry-standard design tools and software
  • Excellent problem-solving skills and the ability to make strategic decisions
  • Experience in leading and driving technical solutions across organization, across function, across geography
  • The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
Job Responsibility
Job Responsibility
  • Driving the development of world class high-performance D2D IPs to enable customer chiplet bases system design win across industries
  • Designing, developing, and evaluating PHY analog components for pre-silicon and post-silicon validation
  • Driving next gen Die to Die IP architecture definition and path finding
  • Customizing PHY designs to meet specific client requirements and performance criteria
  • Performing design trade-offs to optimize power, performance, and area (PPA)
  • Developing and implementing design flows and methodologies to streamline the design process
  • Collaborating with cross-functional teams to ensure seamless integration of analog components with digital systems
  • Providing technical guidance and mentorship to junior engineers and team members
What we offer
What we offer
  • Comprehensive medical and healthcare plans that work for you and your family
  • In addition to company holidays, we have ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Save for your future with our retirement plans that vary by region and country
  • Competitive salaries
  • Fulltime
Read More
Arrow Right