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Digital Functional Verification Engineer

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Teradyne

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Location:
Costa Rica , Alajuela

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Contract Type:
Not provided

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Salary:

Not provided

Job Description:

This is an opportunity for engineering students to complete their professional practice and gain hands on experience with our Costa Rica's engineering team. The digital functional verification intern will work with FPGA verification team and will be responsible for System Verilog and UVM based tests development, running functional simulations, debugging RTL and ensuring functional correctness of FPGA designs. Work under the technical supervision of a Verification Lead. This position is ideal for students pursuing Electrical Engineering, Computer Engineering, or a related discipline who are interested in digital design, verification methodologies, and complex FPGA-based systems.

Job Responsibility:

  • Work with FPGA verification team
  • Responsible for System Verilog and UVM based tests development
  • Running functional simulations
  • Debugging RTL
  • Ensuring functional correctness of FPGA designs
  • Work under the technical supervision of a Verification Lead

Requirements:

  • Must be pursuing a BS degree in Electrical Engineering, Computer Engineering, or a related field
  • Advanced in the study plan and required to be enrolled in a professional practice
  • English Proficient
  • 6 months of experience in: Programming Skills
  • Verilog/System Verilog
  • Simulation tools (e.g., Xcelium, ModelSim, Vivado)
  • Programming skills
  • Simulations tools
  • Scripting (e.g., Python, Bash, Tcl)

Nice to have:

  • Familiarity with FPGA verification flow
  • Familiarity with Digital Functional Verification Methodology (e.g. UVM)
  • Familiarity with version control system (e.g., GIT, clearcase)
  • Knowledge of Industry Standard Protocols (e.g., PCIe, AXI, Ethernet)
  • Great communication skills
  • Proactiveness
  • Problem solving skills

Additional Information:

Job Posted:
April 01, 2026

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