Digital Electronic Integrated Circuit (EIC) Engineer

• Design and implement RTL for datapath, control logic, interfaces, and peripherals (Verilog / SystemVerilog)
• Perform gate-level synthesis, static timing analysis, and constraint validation
• Conduct Lint analysis and logic equivalence checking (LEC)
• Collaborate closely with Functional Verification and Physical Implementation teams
• Apply low-power design techniques and assist with Design for Test considerations

• Minimum 3 years of experience in digital circuit design for SoC/ASIC
• Hands-on experience in RTL architecture, micro-architecture, block-level implementation, and top-level design
• Familiarity with static timing analysis, constraints, Lint, LEC, and low-power estimation
• Experience with SystemVerilog, Verilog, VHDL, Python, TCL, Perl, Linux, GIT
• Exposure to front-end flows of Cadence, Synopsys, or Mentor Graphics

Basic knowledge of Design for Test is a plus

• Opportunity to work on cutting-edge semiconductor projects
• Collaborative, innovation-driven environment
• Competitive compensation and benefits