CrawlJobs Logo

Digital Design Engineer

United States, Sunnyvale 178000.00 - 250000.00 USD / Year · Job Posted March 03, 2026
Apply Position
Job Link Share

Job Description

Meta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning, graphics, display, and network acceleration. You will collaborate with world-class researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.

Job Responsibility

  • Contribute to ASIC digital µArchitecture and design
  • Assist performance/power analysis of the design and help meet power and performance targets
  • Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration
  • Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test
  • Develop micro-architecture, RTL coding, and design verification for complex IPs
  • Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads

Requirements

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
  • Experience in digital design µArchitecture, RTL coding, and micro-architecture development
  • Strong communication and collaboration skills

Nice to have

  • Experience in ML accelerator subsystems and top level design
  • Experience in SoC integration and ASIC architecture
  • Knowledge of microcontrollers, DSP, CDC and power sequence

What we offer

  • bonus
  • equity
  • benefits

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Similar Jobs for

Digital Design Engineer

8 matching positions

Digital Design Engineer

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...
Location
Location
United States , Austin
Salary
Salary:
207335.00 - 234520.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Master’s degree (or foreign degree equivalent) in Computer Engineering, Computer Science, Electrical Engineering, or related field
  • Three years of work experience in job offered or in a digital design or design engineer-related occupation
  • Three years of experience in RTL coding and Logic simulation
  • Three years of experience in Digital design, micro architecture, or VLSI structural design
  • Three years of experience in SystemVerilog or Verilog Hardware description languages
  • Three years of experience in Python, Perl, or similar scripting language
  • Three years of experience in ASIC Design Methodology
  • Three years of experience in Low power design techniques such as clock gating, power gating, memory retention or power-down power states
  • Three years of experience in Digital waveform analysis and C-model based verification of digital circuits
Job Responsibility
Job Responsibility
  • Design and develop state-of-the-art SoC’s, and digital logic IC’s to drive virtual and augmented reality systems
  • Contribute to the development of efficient micro-Architectures and ASIC digital micro-Architecture, design and verification
  • Understand in-house IPs their integration, connection, and verification
  • Drive top-level micro-Architecture definition and develop necessary RTL
  • Drive chip-level integration, verification plan development and verification
  • Supervise RTL-to-GDS flow and assist with synthesis and timing closure
  • Support the test program development, chip validation and chip life until production maturity
  • Work with FPGA engineers to perform early prototyping
  • Support hand-off and integration of blocks into larger SOC environments
  • Assist with algorithm analysis, verification and improvement
What we offer
What we offer
  • bonus
  • equity
  • benefits
  • Fulltime
Read More
Arrow Right

Mixed Signal Digital Design Engineer

Mixed Signal Digital Design Engineer needed: Severn, MD. Must Be Clearable. We h...
Location
Location
United States , Severn
Salary
Salary:
68.00 - 78.00 USD / Hour
geologics.com Logo
GeoLogics
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship and Residency
  • Must Be Clearable
  • W2 hourly Contract Only
  • No 1099
  • No third parties
  • no C2C
  • lead the design, analysis, and verification of high‑speed digital printed‑wire (PW) assemblies
  • familiarity with IPC PCB standards
  • advanced high‑speed digital design techniques
  • expertise in Altium Designer (eCAD)
Job Responsibility
Job Responsibility
  • Lead the design, analysis, and verification of high‑speed digital printed‑wire (PW) assemblies operating in P‑Band (225‑390 MHz), S‑Band (2.4 GHz) and other satellite radar/communication frequency ranges for aerospace and space‑borne platforms (satellites, CubeSats, orbital payloads)
  • mentor junior mixed‑signal PCB designers and champion best‑in‑class design practices
  • Fulltime
Read More
Arrow Right

Staff Digital Design Engineer - DSP

This is an outstanding opportunity for an experienced engineer passionate about ...
Location
Location
United Kingdom , Edinburgh
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proven experience in DSP algorithm development and implementation for SerDes, wireless communications or high-speed serial interfaces (Ethernet, PCIe, etc.)
  • Familiarity with equalization techniques such as FFE, CTLE, DFE or MLSE and their implementation
  • Strong background and experience in digital design techniques including clock domain crossing, RTL (preferably SystemVerilog), and ASIC front-end design tools and flows
  • Understanding of power analysis and techniques for optimization of digital designs for low power
  • Familiarity with simulation and modeling of DSP blocks in SerDes
Job Responsibility
Job Responsibility
  • Collaborate with architects, hardware, and verification engineers to refine and implement new DSP features for cutting-edge and next-generation SerDes transceivers with a focus on low power
  • Implement DSP algorithms for equalization, filtering and sequence detection
  • RTL development and using front-end ASIC tools (lint, synthesis, STA) to ensure the highest quality code
  • Develop comprehensive documentation detailing DSP algorithm interactions with SerDes hardware and software components
  • Fulltime
Read More
Arrow Right

Staff Digital Design Engineer

As a Staff level Design Engineer you will focus on the research, development and...
Location
Location
United Kingdom , Penicuik
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proficient in HDL, design capture and metadata languages (VHDL, System Verilog, C/C++, Python, TCL)
  • Proficient in Digital Signal processing and Linear Algebra
  • Expert in digital design techniques, especially for high speed
  • Experience in digital design, Digital Signal Processing, Linear Algebra
  • Experience in GIT, Perforce, Unix, LSF
  • Familiarity with scripting languages such as Python, Perl, Tcl
  • Bachelors, Masters or PhD in Computer Engineering, Computer Science or Electrical and Electronic Engineering
Job Responsibility
Job Responsibility
  • Research, design, development and productization of DSP and linear algebra IP solutions which target AMD FPGA programmable logic and AMD AIE array processors
  • Verification and validation of these designs
  • Collaboration with peer teams
  • Collaboration for continuous improvement of internal processes and techniques
  • Fulltime
Read More
Arrow Right

Principal Quantum Systems Digital Design Engineer

Microsoft is the world’s center of expertise on topological quantum computing. W...
Location
Location
United States , Redmond
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Electrical/Computer Engineering, or related field AND 3+ years experience in industry or in a research and development environment
  • OR Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 4+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • 6+ years programming experience in related programming languages
  • 6+ years experience in a collaborative environment
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • Ability to work in an "AI first" environment using modern AI tools to accelerate discovery through hardware development
  • Familiarity with designing and building AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval
Job Responsibility
Job Responsibility
  • Design & implement RTL for streaming, low‑latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade‑offs and power/thermal considerations
  • Design and implement high‑speed interconnects between subsystems (AXI4/AXI‑Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring‑up, and throughput/latency tuning
  • Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi‑domain timing closure, async FIFOs, metastability analysis) for deterministic performance
  • Co‑design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams
  • contribute to system‑level design reviews
  • Verification and validation: develop simulation and constrained‑random tests (SV/UVM or equivalent), build on‑board diagnostics (ILA/ChipScope), and execute lab bring‑up with scopes, VNAs, LA/SC, and RF instruments
  • Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign‑off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD
  • Quality & documentation: produce clear design docs, interface specs, and bring‑up guides
  • participate in rigorous code/design reviews and post‑silicon/post‑fabrication retros
  • Fulltime
Read More
Arrow Right

Senior Digital Design Engineer

As a Senior Digital Design Engineer within the ERA RF Technologies engineering t...
Location
Location
Salary
Salary:
Not provided
ERA RF Technologies
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BSEE or MSEE Degree in Electrical Engineering with an emphasis in digital design or communication theory
  • BSEE+10 years or MSEE+8 years of digital design experience
  • In-depth understanding of analytical/mathematical modeling of communication links, ELINT/SIGINT subsystems and related technologies
  • In-depth expertise on VHDL & Verilog Hardware Description Languages
  • Knowledge of RF transceiver architectures and RF-to-Bits comprehension
  • Proficiency on digital communication systems such as modulation, coding, multiple access methodologies and spread spectrum techniques (DSSS, FHSS)
  • Proficiency in written and spoken English
  • Ability to learn and apply new information quickly on solution proposals
  • Ability to embrace technological changes and resultant agile workflows
  • Ability to adapt to multi-disciplinary projects and cross-functional team structures
Job Responsibility
Job Responsibility
  • Contribute to defining and identifying system-level specifications, assessing architectural limitations, and engineering constraints
  • Collaborate with system architects, RF engineers, DSP/algorithm design engineers to understand design requirements and ensure seamless integration of subsystems
  • Characterization and analysis of system architectures
  • Conceptual design from requirement analysis
  • Modelling and simulation of digital design blocks
  • Design, analyze, integration, test and document digital design blocks that meet the reliability objectives, engineering methodologies and guidelines set by avionic, military and spaceborne standards
  • Participate in the requirements analysis phase to determine design feasibility within time, cost, power, and other additional constraints (size, weight, reliability)
  • Recommend enhancements, improvements, innovations, shortcuts and cost savings to the existing technology and design methodology, and propose the development of effective solutions and prototypes, if/when required
Read More
Arrow Right

Asic digital design engineer

Idaho Scientific designs and deploys secure system solutions through novel CPU d...
Location
Location
United States , Boise; Salt Lake City
Salary
Salary:
Not provided
idahoscientific.com Logo
Idaho Scientific
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship (no exceptions)
  • Ability to get a security clearance
  • Solid technical understanding of FPGA or ASIC product development
  • Experience with SystemVerilog, VHDL, and Test-Driven Development principles
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • Extreme attention to detail
  • A willingness to roll up one’s sleeves to get the job done
Job Responsibility
Job Responsibility
  • Collaborate with team leaders to explore and clearly identify real problems and solutions
  • Refine and improve the microarchitecture of Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
  • Integrate complex systems that instantiate both Idaho Scientific and third party IP
  • Contribute to all aspects of design success from specification to production
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world
  • Use high-quality design methods and processes to achieve excellent results
  • Work with other top-notch ASIC design engineers
What we offer
What we offer
  • Competitive Pay
  • Flexible Work Schedule
  • Health Benefits and Insurance
  • Retirement fund contributions
  • Profit Sharing
  • Generous Paid Time Off Policy
  • Fulltime
Read More
Arrow Right

Senior/Principal ASIC Digital Design Engineer

Idaho Scientific designs and deploys secure system solutions through novel CPU d...
Location
Location
United States , Boise; Salt Lake City
Salary
Salary:
Not provided
idahoscientific.com Logo
Idaho Scientific
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship (no exceptions)
  • Proven work experience designing and fabricating an ASIC (no exceptions)
  • Ability to get a security clearance
  • Solid technical background with at least 5 years of experience in FPGA or ASIC product development
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • Extreme attention to detail
  • A willingness to roll up one’s sleeves to get the job done
Job Responsibility
Job Responsibility
  • Collaborate with team leaders to explore and clearly identify real problems and solutions
  • Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
  • Integrate complex systems that instantiate both Idaho Scientific and third party IP
  • Contribute to all aspects of design success from specification to production
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world
  • Define and improve high-quality design methods and processes
  • Mentor and guide other ASIC design engineers
What we offer
What we offer
  • Competitive Pay
  • Flexible Work Schedule
  • Health Benefits and Insurance
  • Retirement fund contributions
  • Profit Sharing
  • Generous Paid Time Off Policy
  • Fulltime
Read More
Arrow Right