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AMD Logo AMD · IT - Software Development

Dft Verification Engineer

India, Bangalore · Job Posted May 13, 2026
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Job Description

We are looking for an adaptive, self-motivated design for test verification engineer to join our growing server SOC DFT team. Identified candidate will be responsible for high quality verification of our DFT features for next generation server SOCs. This team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

Job Responsibility

  • Create and execute test plans for DFT features for next generation EPYC server SOCs
  • Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level
  • Will be creating test bench and verification infra using SV or C++
  • Debug regression test failures and root cause design issues, identify verification gaps and address the same
  • Debug fails and root cause them to design / verification issues
  • Planning and projecting timelines for areas owned such as test plan creation, test writing, development of verification components, pattern generation etc.
  • Collaborate with large set of stakeholders such as architects, design engineers, functional verification engineers, post silicon engineers etc.
  • Work on code and functional coverage
  • Generate patterns for post silicon testing and support ATE bring up
  • Carryout post silicon debugs and help post silicon team achieve high coverage
  • Work on emulation platforms to augment verification

Requirements

  • Prior experience in verifying DFT features at subsystem / SOC level
  • Proficient in standard simulation & debug tools such as VCS, Verdi etc.
  • Experienced with Verilog, C, C++, Linux and Windows environments
  • Bachelors or Masters degree in Electronics/Electrical Engineering

Nice to have

  • Scripting language experience: Perl, Python, Ruby, Makefile, shell
  • Knowledge in few of the DFT features such as JTAG, Memory BIST, Logic BIST, Scan, ATPG
  • Exposure to post silicon debugs and bring up highly desired
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