Dft Verification Engineer Job at AMD (Bangalore)

Staff Engineer - ASIC Development Engineering (DFT)

We are seeking a highly skilled Staff Engineer specializing in ASIC Development ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related field
7+ years of experience in ASIC development with a strong focus on DFT
Advanced knowledge of ASIC design and development processes
Expertise in Design for Testability (DFT) methodologies and techniques
Strong programming skills in languages such as Verilog, VHDL, and C++
Proficiency in using EDA tools for ASIC design, verification, and testing
In-depth understanding of semiconductor manufacturing processes
Experience with advanced DFT techniques, including BIST and ATPG
Knowledge of low-power design techniques
Familiarity with industry standards such as IEEE 1149.1 and IEEE 1500

Job Responsibility

Lead the development and implementation of DFT architectures for complex ASIC designs
Collaborate with cross-functional teams to integrate DFT solutions into the overall ASIC design flow
Develop and optimize test patterns using Automatic Test Pattern Generation (ATPG) tools
Implement Built-In Self-Test (BIST) solutions for various ASIC components
Analyze and improve test coverage, fault coverage, and test time for ASIC designs
Troubleshoot and debug DFT-related issues during the design and post-silicon phases
Stay current with industry trends and emerging DFT technologies
Mentor junior engineers and contribute to the development of best practices and methodologies
Participate in design reviews and provide technical guidance to ensure DFT requirements are met
Collaborate with external partners and vendors to evaluate and integrate new DFT tools and technologies

Fulltime

Staff Product Development Engineer

Staff Test Engineer is responsible for the test solution for a next-generation A...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor/Master in Electrical/Electronic Engineering
Strong hands on experiences in the Semiconductor industry
Strong DFT and ATE test methodologies
End to end ATE Test Prog development, validation and Debug skills including Pre and Post Silicon
Design and review of ATE Hardware (DIB) Design Guidelines
Strong ATE & test class/method development experience with Advantest 93k preferred
Test development experience of more than 1 full product cycle is preferred
Strong Python/Java/Perl/C++ coding skills
Experience with Mentor or Synopsys or Cadence EDA tools or System Level Testing a plus

Job Responsibility

Developing characterization and test coverage strategies/plans during pre-silicon phase
Establishing pattern requirements and driving Design Verification deliveries during pre-silicon phase
Executing the defined characterization and test plans on new silicon
Design Wafer and Package Level Fuse modules for Test Programs
Silicon Bring up and Post Silicon ownership including validation of Test Programs
Perform new device characterization, circuit sensitivity analysis, interpret findings, guide deep-dive investigations to root-cause, and/or provide mitigation actions
Interface with global teams across the organization on root cause resolution for device failures
Foster and develop new ideas/concepts in device test/debug/DFT/DFM and follow-through to deliverable outcomes
Optimize test contents to meet/exceed business goal
Lead effort to optimize product margin to meet business requirements, from Fab to Back-end-Test

Lead Test Development Engineer

Lead the definition and implementation of manufacturing test solutions, developi...

Location

United States , Santa Clara

Salary:

Not provided

Achronix Semiconductor

Expiration Date

Until further notice

Requirements

10+ years of experience in DFT, testing, or silicon validation
Solid understanding of scan insertion, ATPG, MBIST, and fault models
Experience with Synopsys TestMax, Siemens Tessent, and similar DFT EDA tools
Proficiency with JTAG, boundary scan, and related IEEE standards (1149.1, 1149.6)
Hands-on experience with ATPG, MBIST and functional pattern generation, simulation, and verification
Familiarity with script-based test case generators and industry-standard test pattern formats (WGL, STIL)
Proficiency in scripting languages (Python, Perl, or Tcl)
Strong debugging and problem-solving skills for silicon and test issues

Job Responsibility

Define and implement DFT architecture (scan, boundary scan, MBIST)
Collaborate with design and physical design teams to ensure integration and verification of DFT features
Design and implement test mode controls and access mechanisms
Generate and validate ATPG patterns for various fault types
Generate test cases targeting specific FPGA blocks and IP
Work with IP vendors to integrate testing solutions for external memory interfaces and high-speed I/O
Perform fault coverage analysis and implement improvements
Conduct gate-level simulations with test patterns
Perform silicon test pattern bring-up, validation, and debugging on lab bench and ATE platforms
Implement and debug scan, BIST, and functional tests on production testers

Fulltime

New

Senior Quantum Design Verification Engineer

At Microsoft, our mission is to empower every person and every organization on t...

Location

United States , Redmond

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check
proof of citizenship or permanent residency

Job Responsibility

Define pre-silicon Simulation, post-silicon Validation/Characterization plans for SoC/ intellectual property (IP)
coordinate and drive individuals, contingent staff and external vendors towards creating a high-quality design
Own and create verification environments and tests for IP level and SoC level designs
validate designs in simulation with both pre and post layout RTL/netlists
Setup Databases, flows for SoC/IP repositories
Setup Bug-Tracking systems
Drive Milestone reviews, reports/status
Create testplans for pre-silicon simulation verification including for both digital and analog components
performing Analog Mixed Signal Simulation models
Collaborate with Design for Test (DFT) team to test DFT features

Fulltime

Senior Engineer - Design for Test (DFT)

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Hillsboro

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
equivalent experience
4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test
ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check

Job Responsibility

Own block level DFT u-arch specification documentation & provide Test solutions in design for test chips and products
Ensure DFX goals (testability, debug, manufacturability, System Test, System Debug, Repair) are met by these IPs, ensure analog to digital boundaries are reliably tested. Review coverage metrics for Digital logic
Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products, also with the use of AI
Provide test plans and engage closely with verification engineers to perform waveform reviews
Ensure RTL quality pre-DFT to ensure the RTL is good for DFT insertion and coverage
Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis
Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (Architects, front-end & back-end design/verification, Physical design, and post-silicon manufacturing) with respect and with One Microsoft mentality to establish synergies

Fulltime

Dft Design Verification Manager

We are looking for an adaptive, self-motivated DFT design verification engineeri...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proven track record of leading ASIC or SoC design verification teams through successful product tape-outs
Strong expertise in SystemVerilog, UVM, C++ and coverage-driven verification methodologies
Deep understanding of computer architecture, digital logic design
Hands-on experience with EDA tools (Synopsys VCS, Verdi)
Debugging and problem-solving skills for complex, multi-clock domain designs
Strong people management and communication skills to drive geographically distributed projects
Debug test failures to determine the root cause
work with design engineers to resolve design defects and correct any test issues
Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test, and characterization
Design verification experience of High-Speed IO PHY and Controller logic is preferred

Job Responsibility

Design verification of High-Speed IO IP DFT features (e.g., JTAG 1149.x, IJTAG, MBIST, Scan, PRBS, IO Loopback, etc.)
Lead and manage a team of design verification engineers, providing technical direction, mentorship, and performance feedback
Define and drive verification strategy for DFT features, ensuring alignment with architectural goals, schedule, and quality targets
Oversee test plan creation, review, and execution for block- and system-level verification
Collaborate with design, architecture, and ATE engineering teams to resolve complex technical issues and optimize verification approaches
Prioritize and allocate resources across multiple verification tasks and projects, balancing execution speed with quality
Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning

Fulltime

Senior Engineer - Verification

We are seeking skilled SoC (System-on-Chip) ARM Power architecture, Soc clock an...

Location

India , Noida

Salary:

Not provided

ARM

Expiration Date

Until further notice

Requirements

3 - 6 years of proven experience in working on SoC verification environments across Power verification involving multiple power islands and clock and reset verification
Knowledge of assembly language (preferably ARM), C/C++ and hardware verification languages (e.g. SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.)
Experience in one or more of various verification methodologies – UVM/OVM, formal, low power
Good knowledge and working verification experience in Arm M class CPU Processors
Good experience in handling Power aware verification with complex power architecture
Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation and support
Understanding of the fundamentals of Arm system architectures
Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools, UPF, and Debuggers
Experience in working and debugging Soc in DFT mode
Exposure to various front-end verification tools - Questa, VCS, Jasper Gold, Verdi

Job Responsibility

Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules
Responsible for leading a team of engineers to own and power, clk/rst verification for a complex IoT chip
Collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development and build a functional verification strategy
Senior engineers are also encouraged to support mentor junior team members

What we offer

Health and Wellness
Work and Life Success
Financial Rewards
Development and Support

Design For Test Engineer

We are seeking a experienced Design For Test engineer to join our CPU Cores team...

Location

United Kingdom , Cambridge

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in Scan based testing and industry standard ATPG CAD tools
Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc.
Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools
Experience in MBIST implementation and verification
Good understanding of DFT components like JTAG(IEEE 1149.x), IJTAG(IEEE P1687), Core Test(IEEE P1500), SSN(Streaming Scan Network), SSH, Test Compression, OCC etc.
Excellent Verilog RTL coding, scripting( using Python, Perl, Shell, TCL, Awk, Sed etc) and debugging skills
Good understanding of STA concepts
Experience in Spyglass based DFT DRC checks at RTL level
Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc
Prior experience in working with Version control systems like perforce, git etc

Job Responsibility

Keep abreast with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies in to AMD products
Define and implement DFT architecture and features for next generation multi-core microprocessor designs and support their verification effort
Work closely with architects, design, verification, physical design and product engineering teams to integrate DFT requirements seamlessly into the overall design process and to develop scalable DFT architectures for complex CPU designs
Coordinate with DFT teams across different time zones to develop unified DFT strategies, promoting effective communication and collaboration
Work closely with DFT Tool Vendors and drive improvements based on the testability requirements
Develop efficient DFx flows and methodology compatible with front end and back end design flows
Work with the product, test engineering teams and post-silicon debug teams to ensure successful silicon bring up, to help root-cause any silicon failures and to enhance yield learning & improvement
Mentor and coach junior engineers

Fulltime

Dft Verification Engineer

AMD

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
May 13, 2026

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