Dft Engineer Job at AMD (Hyderabad)

Dft Engineer

We are seeking a motivated DFx engineer to join our SOC design team. In this rol...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Experience in scan stitching and strong knowledge of scan stitching concepts
Exposure to MBIST/BISR implementation and the Synopsys SMS MBIST insertion flow
Excellent hands on ATPG experience and familiarity with ATPG related file requirements
Knowledge of Spyglass DFT
Good in C++ and object-oriented programming concepts

Job Responsibility

Implement and verify DFT features such as SCAN, MBIST, and BSCAN
Perform Spyglass DFT bring-up, debug and coverage improvement
Perform scan insertion and ATPG (Traditional, Cell Aware, SSN) pattern generation
Verify ATPG patterns using gate level simulation
Analyze and improve ATPG and DFT DV test coverage
Develop and debug DFT verification tests
Work with the Synthesis and PD team to ensure correct DFT implementation and timing closure
Provide post silicon support to ensure successful bring up

What we offer

AMD benefits at a glance

Fulltime

DFT Engineer

DFT engineer will lead strong engineering team on Scan, MBIST, iJTAG test develo...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience DFT engineering experience through DFT pre and post silicon cycles
Experience in creating and implementing complex chip-level DFT architecture
Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
Strong MBIST knowledge
Knowledge of Tessent Streaming Scan Network SSN and hand-on experience is a big plus
Proficient in logic design using Verilog and experience in synthesis and STA
Experience in developing test benches and simulation in RTL/GATE/SDF environments
Knowledge of FPGA synthesis and design flow is a plus
Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)

Job Responsibility

Manage DFT engineers resolving technical challenges and meeting product schedule
The role is in AMD global quality and operation organization driving best manufacturing test solution through pre and post silicon activities
Work closely with design teams and make sure DFT structures are correctly implemented
Responsible for developing, implementing and verifying DFT schemes on hard-IPs in AMD ASIC and FPGA products
Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, IEEE1149.1 JTAG and IEEE1687 IJTAG
Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE
Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem
Assist in Diagnosis and Yield enhancement through product lifecycle
Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management

Fulltime

Senior Dft Engineer

AECG ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded ...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

6 years of DFT design, integration, verification, ATPG and Silicon Debug experience
Demonstrated technical leadership and works well with cross-functional teams
Excellent communication and interpersonal skills
Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design
Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc
Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential
Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
Experience in solving logic design or timing issues with integration, synthesis and PD teams
Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl)
Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis

Job Responsibility

Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology
Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows
Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS
Writing and maintain DFT documentation and specifications
Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design
Performing scan insertion, ATPG verification and test pattern generation
Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis

Fulltime

Senior DFT Engineer

As a member of the Radeon Technologies Group, you will help bring to life cuttin...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Implementation and verification of DFT architecture and features
Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Fulltime

Senior Dft Engineer

As a member of the Radeon Technologies Group, you will help bring to life cuttin...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Implementation and verification of DFT architecture and features
Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Fulltime

New

Senior DFT Design Engineer (ATPG/Scan stitching)

We are looking for an adaptive, self-motivative DFT engineer to join our growing...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering
Experience in scan-stitching
and has good knowledge of scan-stitching related concepts
Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion
Excellent hands-on ATPG
and is well conversed with the files required to run ATPG
Knowledge/experience with Tessent ATPG (mentor) is a plus
Knowledge on Spyglass-DFT
Excellent hands-on debug skills and scripting skills are critical
Knowledge on automation scripts like TCL/AWK/SED is a plus

Job Responsibility

Implementation and verification of DFT features like SCAN, MBIST, LBIST and JTAG
Support Spyglass-DFTDRC debug and coverage correlation
Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Fulltime

Sr. DFT Design Engineer

Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. A...

Location

United States , Austin

Salary:

159200.00 - 215300.00 USD / Year

Amazon Pforzheim GmbH

Expiration Date

Until further notice

Requirements

Bachelor's degree in computer science, electrical engineering, or related field
5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks experience
Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
Experience with automation script development

Job Responsibility

Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals
Mentor and develop junior engineers through code reviews, methodology training, and technical guidance
Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up

What we offer

health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
401(k) matching
paid time off
parental leave
sign-on payments
restricted stock units (RSUs)

Fulltime

Dft Verification Engineer

We are looking for an adaptive, self-motivated design for test verification engi...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Prior experience in verifying DFT features at subsystem / SOC level
Proficient in standard simulation & debug tools such as VCS, Verdi etc.
Experienced with Verilog, C, C++, Linux and Windows environments
Bachelors or Masters degree in Electronics/Electrical Engineering

Job Responsibility

Create and execute test plans for DFT features for next generation EPYC server SOCs
Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level
Will be creating test bench and verification infra using SV or C++
Debug regression test failures and root cause design issues, identify verification gaps and address the same
Debug fails and root cause them to design / verification issues
Planning and projecting timelines for areas owned such as test plan creation, test writing, development of verification components, pattern generation etc.
Collaborate with large set of stakeholders such as architects, design engineers, functional verification engineers, post silicon engineers etc.
Work on code and functional coverage
Generate patterns for post silicon testing and support ATE bring up
Carryout post silicon debugs and help post silicon team achieve high coverage

Fulltime

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