Dft Engineer Job at AMD (Penang)

DFT Engineer

DFT engineer will lead strong engineering team on Scan, MBIST, iJTAG test develo...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience DFT engineering experience through DFT pre and post silicon cycles
Experience in creating and implementing complex chip-level DFT architecture
Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
Strong MBIST knowledge
Knowledge of Tessent Streaming Scan Network SSN and hand-on experience is a big plus
Proficient in logic design using Verilog and experience in synthesis and STA
Experience in developing test benches and simulation in RTL/GATE/SDF environments
Knowledge of FPGA synthesis and design flow is a plus
Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)

Job Responsibility

Manage DFT engineers resolving technical challenges and meeting product schedule
The role is in AMD global quality and operation organization driving best manufacturing test solution through pre and post silicon activities
Work closely with design teams and make sure DFT structures are correctly implemented
Responsible for developing, implementing and verifying DFT schemes on hard-IPs in AMD ASIC and FPGA products
Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, IEEE1149.1 JTAG and IEEE1687 IJTAG
Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE
Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem
Assist in Diagnosis and Yield enhancement through product lifecycle
Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management

Fulltime

Senior DFT Engineer

As a member of the Radeon Technologies Group, you will help bring to life cuttin...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Implementation and verification of DFT architecture and features
Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Fulltime

Senior Dft Engineer

As a member of the Radeon Technologies Group, you will help bring to life cuttin...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Implementation and verification of DFT architecture and features
Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Fulltime

Sr. DFT Design Engineer

Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. A...

Location

United States , Austin

Salary:

159200.00 - 215300.00 USD / Year

Amazon Pforzheim GmbH

Expiration Date

Until further notice

Requirements

Bachelor's degree in computer science, electrical engineering, or related field
5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks experience
Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
Experience with automation script development

Job Responsibility

Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals
Mentor and develop junior engineers through code reviews, methodology training, and technical guidance
Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up

What we offer

health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
401(k) matching
paid time off
parental leave
sign-on payments
restricted stock units (RSUs)

Fulltime

Dft Verification Engineer

We are looking for an adaptive, self-motivated design for test verification engi...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Prior experience in verifying DFT features at subsystem / SOC level
Proficient in standard simulation & debug tools such as VCS, Verdi etc.
Experienced with Verilog, C, C++, Linux and Windows environments
Bachelors or Masters degree in Electronics/Electrical Engineering

Job Responsibility

Create and execute test plans for DFT features for next generation EPYC server SOCs
Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level
Will be creating test bench and verification infra using SV or C++
Debug regression test failures and root cause design issues, identify verification gaps and address the same
Debug fails and root cause them to design / verification issues
Planning and projecting timelines for areas owned such as test plan creation, test writing, development of verification components, pattern generation etc.
Collaborate with large set of stakeholders such as architects, design engineers, functional verification engineers, post silicon engineers etc.
Work on code and functional coverage
Generate patterns for post silicon testing and support ATE bring up
Carryout post silicon debugs and help post silicon team achieve high coverage

Fulltime

Cad Front End And Dft Flows Engineer

At AMD, our mission is to build great products that accelerate next-generation c...

Location

India , Hyderabad; Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Master’s/Bachelor’s Degree in Electronics or Computer Engineering
4-6 years of experience in CAD flow and methodology development on advanced technology nodes
Hands on experience in front end and DFT flows
Hands on experience in industry standard Design tools such as Lint, CDC, RDC tools and DFT tools
Good knowledge on scripting languages like Python, PERL, TCL and strong debug capabilities
CAD and Automation mindset

Job Responsibility

Responsible for developing Front-end Design, synthesis and DFT methodologies for various designs at advanced technology nodes
Collaborate with the design team to drive continuous improvements in DFT and front-end design methodologies, ensuring top-quality RTL and Netlist across areas different areas such as Lint, CDC, formal verification, DFT coverage
Script out utilities to automate different pieces of the flows
Enhance and develop flows that enable for AMD's next-generation monolithic and stacked FPGA-SoC product families
Leverage corporate AI systems to increase productivity and streamline workflows

Fulltime

Dft Silicon Design Engineer

AECG SSD ASIC is a centralized ASIC design group within AMD's Adaptive and Embed...

Location

India , New Delhi

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST
Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
Familiar with Verilog design language, Verilog simulator and waveform debugging tools
Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus
Strong problem-solving skills
Team player with strong communication skills
Bachelor's or Master's degree in electrical/Electronic Engineering

Job Responsibility

Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications
Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS
Work with multi-functional teams and handling schedules
Debugging and verifying block-/chip-level DFT/DFX features
Porting or creating the DFT/DFX verification environment
Block/chip test plan creation and development
Stimulus writing and debug, and regression clean-up
Generating high quality manufacturing test patterns for stuck-at, transition fault models and using on-chip test compression techniques
Simulating and verifying the ATPG and LBIST patterns
Working with the product engineering teams on the delivery of manufacturing test patterns

Fulltime

NPI DFT Process Development Engineer - AI/ML

Join an NPI‑focused team, building innovative test processes and automation for ...

Location

United States , Deer Park

Salary:

76600.00 - 122500.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

B.S. in Engineering (Electrical Engineering/Engineering Technology or related disciplines)
2+ years in Process / Test / NPI Engineering
Exposure to ML (Machine Learning)/analytics for manufacturing (e.g., anomaly detection on test logs, simple classifiers in scikit‑learn)
Basic LLM (Large Language Models) tooling (prompting, retrieval on test knowledge base) to speed triage & documentation
Experience with platform integration across various Digital/AC/DC/RF modules
Hands‑on with lab/instrumentation (oscilloscopes, DMMs
RF gear such as VNA, spectrum analyzers is a plus)
Read/interpret schematics, datasheets
troubleshoot to component level.
Scripting for automation (Python/Perl

Job Responsibility

Design & implement test strategies from module to system level aligned with manufacturing flows (DfT)
collaborate across SW/HW/Pilot/Operations to validate and transfer into Pilot through HVM.
Develop automated test solutions (Python/Perl/C#/VB.NET) and basic data pipelines (SQL/Power BI) to monitor yield/CPK, drive FA/RCCA, and shorten detection/diagnosis cycles.
Evaluate prototypes and finished units for functionality and conformance
perform bring‑up, integration, and debug.
Contribute to standards: fixtures, calibration strategies, documentation, and best practices.
Support transfers by training pilot/production teams and providing on‑site support during ramps.

What we offer

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.
This job is eligible for discretionary bonus(es) based on financial performance.

Fulltime

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Dft Engineer

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