Dft engineer Jobs

New

Staff Engineer - ASIC Development Engineering (DFT)

We are seeking a highly skilled Staff Engineer specializing in ASIC Development ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related field
7+ years of experience in ASIC development with a strong focus on DFT
Advanced knowledge of ASIC design and development processes
Expertise in Design for Testability (DFT) methodologies and techniques
Strong programming skills in languages such as Verilog, VHDL, and C++
Proficiency in using EDA tools for ASIC design, verification, and testing
In-depth understanding of semiconductor manufacturing processes
Experience with advanced DFT techniques, including BIST and ATPG
Knowledge of low-power design techniques
Familiarity with industry standards such as IEEE 1149.1 and IEEE 1500

Job Responsibility

Lead the development and implementation of DFT architectures for complex ASIC designs
Collaborate with cross-functional teams to integrate DFT solutions into the overall ASIC design flow
Develop and optimize test patterns using Automatic Test Pattern Generation (ATPG) tools
Implement Built-In Self-Test (BIST) solutions for various ASIC components
Analyze and improve test coverage, fault coverage, and test time for ASIC designs
Troubleshoot and debug DFT-related issues during the design and post-silicon phases
Stay current with industry trends and emerging DFT technologies
Mentor junior engineers and contribute to the development of best practices and methodologies
Participate in design reviews and provide technical guidance to ensure DFT requirements are met
Collaborate with external partners and vendors to evaluate and integrate new DFT tools and technologies

Fulltime

New

Staff Product Development Engineer

Staff Test Engineer is responsible for the test solution for a next-generation A...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor/Master in Electrical/Electronic Engineering
Strong hands on experiences in the Semiconductor industry
Strong DFT and ATE test methodologies
End to end ATE Test Prog development, validation and Debug skills including Pre and Post Silicon
Design and review of ATE Hardware (DIB) Design Guidelines
Strong ATE & test class/method development experience with Advantest 93k preferred
Test development experience of more than 1 full product cycle is preferred
Strong Python/Java/Perl/C++ coding skills
Experience with Mentor or Synopsys or Cadence EDA tools or System Level Testing a plus

Job Responsibility

Developing characterization and test coverage strategies/plans during pre-silicon phase
Establishing pattern requirements and driving Design Verification deliveries during pre-silicon phase
Executing the defined characterization and test plans on new silicon
Design Wafer and Package Level Fuse modules for Test Programs
Silicon Bring up and Post Silicon ownership including validation of Test Programs
Perform new device characterization, circuit sensitivity analysis, interpret findings, guide deep-dive investigations to root-cause, and/or provide mitigation actions
Interface with global teams across the organization on root cause resolution for device failures
Foster and develop new ideas/concepts in device test/debug/DFT/DFM and follow-through to deliverable outcomes
Optimize test contents to meet/exceed business goal
Lead effort to optimize product margin to meet business requirements, from Fab to Back-end-Test

Lead Test Development Engineer

Lead the definition and implementation of manufacturing test solutions, developi...

Location

United States , Santa Clara

Salary:

Not provided

Achronix Semiconductor

Expiration Date

Until further notice

Requirements

10+ years of experience in DFT, testing, or silicon validation
Solid understanding of scan insertion, ATPG, MBIST, and fault models
Experience with Synopsys TestMax, Siemens Tessent, and similar DFT EDA tools
Proficiency with JTAG, boundary scan, and related IEEE standards (1149.1, 1149.6)
Hands-on experience with ATPG, MBIST and functional pattern generation, simulation, and verification
Familiarity with script-based test case generators and industry-standard test pattern formats (WGL, STIL)
Proficiency in scripting languages (Python, Perl, or Tcl)
Strong debugging and problem-solving skills for silicon and test issues

Job Responsibility

Define and implement DFT architecture (scan, boundary scan, MBIST)
Collaborate with design and physical design teams to ensure integration and verification of DFT features
Design and implement test mode controls and access mechanisms
Generate and validate ATPG patterns for various fault types
Generate test cases targeting specific FPGA blocks and IP
Work with IP vendors to integrate testing solutions for external memory interfaces and high-speed I/O
Perform fault coverage analysis and implement improvements
Conduct gate-level simulations with test patterns
Perform silicon test pattern bring-up, validation, and debugging on lab bench and ATE platforms
Implement and debug scan, BIST, and functional tests on production testers

Fulltime

Asic Engineer Sr Staff

Hewlett Packard Enterprise is seeking a seasoned Design-for-Test (DFT) Engineer ...

Location

United States , San Jose

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains
deep understanding of fault models: stuck-at, transition, path-delay
expertise in scan compression, ATPG, and MBIST architecture
experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair
proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler
simulation experience with Synopsys VCS and Cadence NC-Verilog
timing analysis using PrimeTime and Cadence Tempus
able to define test constraints and review STA reports to ensure timing closure in test modes
debugging with waveform tools such as Novas and SimVision
familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF

Job Responsibility

define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond
collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features
develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models
analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations
apply test constraints and perform STA analysis to ensure timing closure in test modes
support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF)
conduct silicon failure analysis and contribute to system-level debug and yield improvement
automate DFT flows and analysis using scripting languages such as Perl and Tcl.

What we offer

health & wellbeing
personal & professional development
unconditional inclusion
competitive compensation, benefits, and career growth opportunities.

Fulltime

Manufacturing Test Engineer, PCBA

Figure is an AI robotics company developing autonomous general-purpose humanoid ...

Location

United States , San Jose

Salary:

160000.00 - 250000.00 USD / Year

Figure

Expiration Date

Until further notice

Requirements

5+ years of experience in PCBA manufacturing test, ideally with high-complexity boards and tight timelines
Hands-on experience with ICT and FCT system design, bed-of-nails fixture development, and board-level debug
Strong understanding of DFT (Design for Testability) and how to collaborate with EE/FW teams early in the design cycle
Experience working directly with overseas CMs and test vendors
Familiarity with test automation frameworks, data collection, and reporting tools
Able to read schematics, probe/debug hardware, and communicate clearly across disciplines
Strong proficiency in writing Python for interfacing with real hardware
Willingness to travel overseas 40% of the time

Job Responsibility

Own test coverage strategy for all custom PCBAs across the product
Design, validate, and deploy bed-of-nails ICT and FCT test fixtures, working directly with overseas test vendors and fixture houses
Collaborate with electrical and firmware teams to define test hooks, firmware test modes, and diagnostics coverage
Specify and validate test software, including automated test sequencing, result logging, and failure triage
Serve as the test lead on-site at CMs during NPI builds to bring up, debug, and improve test coverage and throughput
Monitor test yield data, drive root cause analysis for failures, and recommend corrective actions
Act as the first line of defense when boards or testers start failing
Ensure test processes scale from EVT through MP, with clear handoff documentation and ongoing vendor support

Fulltime

New

Hardware Design Engineering Intern/Co-op

We are seeking a highly motivated Hardware Design engineering intern/co-op to jo...

Location

Canada , Markham

Salary:

65000.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Currently enrolled in a Canada based University into a Bachelor's degree program majoring in Electrical engineering or Computer engineering or a related field
Strong semiconductor device physics knowledge
Digital /Logic circuits and VLSI
Verilog or VHDL hardware description languages
Exposure to UVM methodologies
Scripting languages (e.g. Python, Perl, TCL, Ruby), Shell / UNIX scripting, C/C++, MATLAB
Interest or experience in Machine Learning
ASIC design
Knowledge of Ruby on Rails and MySQL
Linux/Unix environment

Job Responsibility

Collaborate with Design Engineers on the physical design verification and physical implementation for some of our ASIC
Work on Memory interface simulation work eg. GDDR7, HBM, UCIE
Work on Discreate and Embedded hardware products and chip to chip interconnect
Actively participate in RTL design in Verilog
Synthesis with timing driven placement and design for power (DFP)
Floor planning, Power distribution, Clock distribution, Block/Chip Place & Route, EM/IR analysis, Timing closure, Static Timing Analysis
Analysis of logical equivalent check, RTL clocking analysis, static power analysis, and design for test (DFT)
Build test libraries and models by using advanced verification languages such as System Verilog, UVM and C++

Fulltime

New

Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical i...

Location

United States , Batavia, Illinois

Salary:

Not provided

NHanced Semiconductors

Expiration Date

Until further notice

Requirements

US Citizenship
5+ years of experience in physical design, specifically in ASIC, SoC, or advanced packaging (2.5D, 3DIC) technologies
Hands-on experience with Git-based version control systems for managing design revisions
Experience with timing closure and signal integrity
Proficiency in Cadence tools for physical design, timing analysis, and signoff
Strong understanding of RTL-to-GDSII flows, including floorplanning, power planning, place-and-route, and timing closure
Working knowledge of parasitic extraction (PEX), power integrity (PI), and thermal analysis in multi-die environments
Ability to work independently with minimal supervision and drive tasks to completion
Excellent verbal and written communication skills for collaboration across engineering teams
Strong debugging skills and ability to analyze tool reports, logs, and simulation results

Job Responsibility

Drive full-chip physical implementation of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
Ensure design compliance with timing, power, and area (PPA) requirements, as well as DFM, DRC, and LVS constraints
Utilize Cadence tools (Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff
Develop and execute timing closure strategies, working with STA engineers to meet performance goals
Optimize power distribution networks (PDN) and electromigration (EM) reliability in multi-die packaging environments
Work with package and system engineers to optimize die-to-die interconnect, bump placement, and TSV integration
Collaborate with RTL designers, DFT engineers, and backend teams to ensure seamless integration
Implement ECOs (Engineering Change Orders) and efficiently iterate design revisions
Utilize Git-based version control workflows for design database management and collaborative development
Identify and resolve congestion, signal integrity (SI), and crosstalk issues in complex designs

New

Senior Digital RTL2GDSII Implementation Engineer

Palma Ceia SemiDesign (PCS), is a fast-growing, fabless semiconductor company, f...

Location

United Kingdom , Cambridge

Salary:

Not provided

Palma Ceia SemiDesign

Expiration Date

Until further notice

Requirements

Bachelor’s degree in electronic engineering or a related subject
Proficient in either front-end or back-end implementation tools (either Cadence or Synopsys based flows)
Proven ability to perform complex digital implementation tasks in an SoC context
Familiarity with design for test issues, packaging issues, and low power methodologies
Good written and verbal communication skills
Strong team-player
Can-do attitude
Mind-set to produce high quality, maintainable work
A willingness to get involved in whatever needs doing

Job Responsibility

Work with digital design engineers and other RTL2GDSII engineers to produce highly optimized, power efficient, area efficient digital implementations for integration into SoCs
Could be front-end focused (synthesis, DFT insertion, constraints, LEC) or back-end focused (floor-planning, place & route, STA, DRC/LVS) depending on experience
Work with design engineers and packaging engineers to ensure a high performance and cost effective overall SoC solution
Potential for involvement in digital RTL design if candidate also has experience in this area
Peer review of colleagues’ work

Dft engineer

AMD

Location:
China, Shanghai

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
December 17, 2025

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