Dft/dfx Engineer

• Own/lead the DFX Design Architect
• Develop and implement cutting edge DFX features including SCAN, ATPG, MBIST, BSCAN, etc
• Work closely with the DFX Architecture and the various IP Design teams to align on the DFX requirements and successfully implement the DFX design
• Design and develop correct by construction DFX design and support DFX verification
• Work closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects
• Work with the Synthesis and PD team to ensure correct DFT implementation in Scan/ATPG

• Experience and understanding of ASIC DFX
• Scan synthesis
• Integration flow using Fusion Compiler
• ATPG experience in tile and SoC level
• Familiar with scan hardware compressions, failure mechanisms and debug processes
• Familiar in ICl Extraction, SSN, IJTAG, EDT, TestKompress, simulation and verification flow
• Experience of working in DFX architecture of complex SOC
• Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem
• Experience in End-to-End DFX flow development/creation
• DC/AC scan (at-speed) development, debug and test
• Expert in at least one scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts
• Strong EDA tools experience Tessent - Testkompress, SSN, IJTAG, Synopsys - Fusion compiler, Design Compiler, Spyglass
• Experience with RTL quality check tools/methodologies such as Spyglass, Lint
• Exposure to Static timing analysis & Timing closure
• Scan/ATPG patterns & test flows development, debug, test, and characterization
• Excellent hands-on debug skills and scripting skills
• Strong communication skills and ability to collaborate effectively within a global team
• Strong problem-solving skills
• Bachelors or Masters degree in computer engineering/Electrical Engineering

Knowledge & experience of low power concepts, clock gating, power gating