Dft Design Verification Manager

• Design verification of High-Speed IO IP DFT features (e.g., JTAG 1149.x, IJTAG, MBIST, Scan, PRBS, IO Loopback, etc.)
• Lead and manage a team of design verification engineers, providing technical direction, mentorship, and performance feedback
• Define and drive verification strategy for DFT features, ensuring alignment with architectural goals, schedule, and quality targets
• Oversee test plan creation, review, and execution for block- and system-level verification
• Collaborate with design, architecture, and ATE engineering teams to resolve complex technical issues and optimize verification approaches
• Prioritize and allocate resources across multiple verification tasks and projects, balancing execution speed with quality
• Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning

• Proven track record of leading ASIC or SoC design verification teams through successful product tape-outs
• Strong expertise in SystemVerilog, UVM, C++ and coverage-driven verification methodologies
• Deep understanding of computer architecture, digital logic design
• Hands-on experience with EDA tools (Synopsys VCS, Verdi)
• Debugging and problem-solving skills for complex, multi-clock domain designs
• Strong people management and communication skills to drive geographically distributed projects
• Debug test failures to determine the root cause
• work with design engineers to resolve design defects and correct any test issues
• Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test, and characterization
• Design verification experience of High-Speed IO PHY and Controller logic is preferred

Design verification experience of High-Speed IO PHY and Controller logic is preferred