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The CIT team is a dynamic and innovative team dedicated to pushing the boundaries of hardware development. We are seeking skilled and motivated verification engineers to join our growing team and to contribute to the success of cutting-edge IPs. We are currently looking for an experienced ASIC Design Verification engineer who will be involved in all aspects of design verification activities, using the latest methodologies with the help of automation, keeping power and performance in mind. The candidate will utilize/develop a variety of verification components, using the latest verification methodologies to achieve an excellent RTL/Firmware design quality.
Job Responsibility:
Closely work with architects and designers to develop verification strategies and execution plans
Participate in the verification of complex IP blocks, take end to end ownership of key features for all projects
Work on test plans, test case development, testbench enhancement, regression, and coverage closure
Deploying industry-leading verification methodologies, such as UVM and Formal Verification
Developing testbenches and verification components such as UVCs, models, BFMs, and re-usable verification environments
Writing, modifying, and maintaining constraint-random and directed test cases and libraries in System Verilog/UVM
Analyzing functional, code, and test plan coverage
Implementing assertions, checkers, and monitors
Triaging and debugging regressions
Reproducing functional bugs found in silicon, in simulation and/or Formal Verification tools
Conducting and participating in code reviews
Requirements:
Extensive hardware verification experience
Must be proficient in Verilog, System Verilog, UVM, and working in Linux and Windows environments
Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools
Must have excellent programming skills
Must have exposure to Makefile and other scripting languages like Perl, Python and Ruby
Electrical Engineering or Computer Engineering education