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Definition, documentation, development, and execution of simulation based verification test for compiler tool, able to run on any available RTL simulator (Cadence, Synopsys, Siemens)
Definition, documentation, development, and execution of validation tests using Python scripting for qualifying additional Register tool collaterals (IP-XACT, C Header files, Documentation)
Maintain and enhance tests in the continuous integration flow, improve metrics, and increase automation
Help improve and refine processes, methodologies, and metrics
Be familiar with modern tools for specifications/documentation, tasks and project tracking (like Confluence and Jira)
Internal/external working relationships
Collaborate with developers to identify testing needs and scenarios specific to EDA
Participate in code reviews and unit testing with other developers to ensure code quality
Requirements:
7+ years of industry experience as an RTL Verification Engineer
Strong expertise with the UVM verification framework
Solid understanding of hardware RTL design languages: VHDL, Verilog, SystemVerilog
Proficiency in Python for scripting and automation
Good written and verbal communication skills in English
Curious, autonomous, rigorous, and delivery-oriented, with strong attention to quality and detail
Engineering degree in Computer Science, Electronics, or a related field
Fluent English
Nice to have:
French proficiency
knowledge of IP-XACT, C-HAL, and equivalence checking tools