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The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.
Job Responsibility
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Requirements
Bachelors or Masters degree in computer engineering/Electrical Engineering
Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Developing UVM based verification frameworks and testbenches, processes and flows
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Assembly-level debugging ability
Scripting proficiency in Perl or Python (shell/Makefile/Ruby beneficial)
Proficient in using UVM testbenches and working in Linux and Windows environments
Practical experience with functional and code coverage analysis and closure
Automating workflows in a distributed compute environment
Build and improve verification frameworks, regression quality, and automation workflows
Nice to have
Exposure to leadership or mentorship is an asset
Solves complex, novel, and non-recurring problems
Initiates and leads significant method/process improvements
Owns processes of significant technical importance, including outcomes in own area and interdependent areas