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Meta Logo Meta · IT - Software Development

Design Verification Engineer

United States, Sunnyvale 146000.00 - 209000.00 USD / Year · Job Posted January 23, 2026
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Job Description

Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

Job Responsibility

  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
  • Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Requirements

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
  • 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Nice to have

  • Experience with revision control systems like Mercurial(Hg), Git or SVN
  • Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
  • Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch
  • Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation
  • Prior working knowledge of Audio/image/Video processing compute intensive cores

What we offer

  • bonus
  • equity
  • benefits
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