Design Verification Engineer

• Identify formal friendly modules/features across Data Fabric unit/subsystem and work with different stake holders in getting a thorough understanding of microarch/high level spec and get clarification (if any)
• Evaluate cross-feature/cross-unit dependency impact
• Populate detailed testplan (planned checks, abstraction, coverage) post feature analysis and get it reviewed & incorporate feedback
• Create Formal Testbench with assertions/assumptions with necessary level of abstraction in place to verify a complete feature
• Debug failures to root cause issues/fix constraints, deal with tool issues efficiently in collaboration with concerned AE from Synopsys/Cadence
• On a need basis, work on Post-Si bug recreation
• On a need basis, work on Flow automation related to Formal flow

• 7+ years of experience on Formal verification on Complex IP's
• Proficiency in overall Formal Verification methodology with tools like (VC-FORMAL/JASPER)
• Proficiency in creating testplans, building formal testbenches from scratch
• Good understanding about computer architecture/microarchitecture and ability to deal with complex sequential logic and datapath
• Good understanding of Verilog, System Verilog, SVA
• Some knowledge of shell/perl/python scripting is a plus
• Should have leadership quality, quick thinker, pro-active, adaptable & outspoken/approachable
• Must communicate well both written and orally
• Must be well-organized and should be able to multitask well with due diligence on closing his/her tasks
• Bachelor’s or master’s degree in Electronics or Electrical or Computer engineering

Some knowledge of shell/perl/python scripting is a plus

AMD benefits at a glance