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We are seeking a motivated Junior Verification Engineer to join our team focused on verifying AMD’s PCIe Bus Functional Model (BFM) by interfacing with the third party PCIe BFM using PIPE mode. This is an excellent opportunity for a new graduate or early-career engineer to gain hands-on experience in high-speed interface verification, PCIe protocol, and advanced verification methodologies.
Job Responsibility:
Assist in developing and maintaining a UVM-based testbench environment to verify AMD PCIe BFM interoperability with Avery PCIe BFM over PIPE interface
Write and execute test sequences to validate PCIe protocol compliance, data integrity, flow control, and error handling
Collaborate with senior engineers to debug issues, analyze simulation results, and improve test coverage
Support integration of the testbench with RTL designs for comprehensive verification
Participate in design and code reviews and contribute to continuous improvement of verification processes
Document test plans, results, and verification status clearly and effectively
Requirements:
Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or related field
Strong interest in digital design verification and high-speed interfaces
Good problem-solving skills and attention to detail
Effective communication skills and ability to work collaboratively in a team environment
Eagerness to learn and adapt in a fast-paced technical environment
Nice to have:
Familiarity with System Verilog and UVM
Understanding of PCIe protocol fundamentals
Internship or project experience related to digital verification and PCIe
Exposure to scripting languages (Python, Perl, TCL) for automation
Basic knowledge of PIPE interface or high-speed serial protocols